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Revert "[AArch64][FastISel] Add more truncation tests." and "[AArch64][FastISel] Always use an AND instruction when truncating to non-legal types."
This reverts commit r243198 and 243304. Turns out this wasn't the correct fix for this problem. It works only within FastISel, but fails when the truncate is selected by SDAG. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244287 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka
parent
3153f23b24
commit
6f653ee44c
@ -3794,34 +3794,41 @@ bool AArch64FastISel::selectTrunc(const Instruction *I) {
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return false;
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bool SrcIsKill = hasTrivialKill(Op);
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// If we're truncating from i64/i32 to a smaller non-legal type then generate
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// an AND.
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uint64_t Mask = 0;
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switch (DestVT.SimpleTy) {
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default:
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// Trunc i64 to i32 is handled by the target-independent fast-isel.
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return false;
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case MVT::i1:
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Mask = 0x1;
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break;
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case MVT::i8:
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Mask = 0xff;
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break;
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case MVT::i16:
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Mask = 0xffff;
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break;
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}
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// If we're truncating from i64 to a smaller non-legal type then generate an
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// AND. Otherwise, we know the high bits are undefined and a truncate only
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// generate a COPY. We cannot mark the source register also as result
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// register, because this can incorrectly transfer the kill flag onto the
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// source register.
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unsigned ResultReg;
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if (SrcVT == MVT::i64) {
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uint64_t Mask = 0;
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switch (DestVT.SimpleTy) {
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default:
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// Trunc i64 to i32 is handled by the target-independent fast-isel.
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return false;
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case MVT::i1:
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Mask = 0x1;
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break;
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case MVT::i8:
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Mask = 0xff;
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break;
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case MVT::i16:
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Mask = 0xffff;
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break;
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}
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// Issue an extract_subreg to get the lower 32-bits.
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SrcReg = fastEmitInst_extractsubreg(MVT::i32, SrcReg, SrcIsKill,
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AArch64::sub_32);
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SrcIsKill = true;
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unsigned Reg32 = fastEmitInst_extractsubreg(MVT::i32, SrcReg, SrcIsKill,
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AArch64::sub_32);
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// Create the AND instruction which performs the actual truncation.
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ResultReg = emitAnd_ri(MVT::i32, Reg32, /*IsKill=*/true, Mask);
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assert(ResultReg && "Unexpected AND instruction emission failure.");
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} else {
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ResultReg = createResultReg(&AArch64::GPR32RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), ResultReg)
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.addReg(SrcReg, getKillRegState(SrcIsKill));
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}
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// Create the AND instruction which performs the actual truncation.
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unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, SrcIsKill, Mask);
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assert(ResultReg && "Unexpected AND instruction emission failure.");
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updateValueMap(I, ResultReg);
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return true;
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}
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@ -363,8 +363,7 @@ entry:
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define i32 @i64_trunc_i32(i64 %a) nounwind ssp {
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entry:
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; CHECK-LABEL: i64_trunc_i32
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; CHECK: mov [[REG:x[0-9]+]], x0
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; CHECK-NEXT: mov x0, [[REG]]
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; CHECK: mov x1, x0
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%conv = trunc i64 %a to i32
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ret i32 %conv
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}
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@ -372,9 +371,9 @@ entry:
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define zeroext i16 @i64_trunc_i16(i64 %a) nounwind ssp {
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entry:
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; CHECK-LABEL: i64_trunc_i16
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; CHECK: mov x[[REG:[0-9]+]], x0
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; CHECK-NEXT: and [[REG2:w[0-9]+]], w[[REG]], #0xffff
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; CHECK-NEXT: uxth w0, [[REG2]]
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; CHECK: mov x[[REG:[0-9]+]], x0
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; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0xffff
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; CHECK: uxth w0, [[REG2]]
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%conv = trunc i64 %a to i16
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ret i16 %conv
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}
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@ -382,9 +381,9 @@ entry:
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define zeroext i8 @i64_trunc_i8(i64 %a) nounwind ssp {
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entry:
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; CHECK-LABEL: i64_trunc_i8
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; CHECK: mov x[[REG:[0-9]+]], x0
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; CHECK-NEXT: and [[REG2:w[0-9]+]], w[[REG]], #0xff
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; CHECK-NEXT: uxtb w0, [[REG2]]
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; CHECK: mov x[[REG:[0-9]+]], x0
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; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0xff
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; CHECK: uxtb w0, [[REG2]]
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%conv = trunc i64 %a to i8
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ret i8 %conv
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}
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@ -392,67 +391,13 @@ entry:
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define zeroext i1 @i64_trunc_i1(i64 %a) nounwind ssp {
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entry:
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; CHECK-LABEL: i64_trunc_i1
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; CHECK: mov x[[REG:[0-9]+]], x0
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; CHECK-NEXT: and [[REG2:w[0-9]+]], w[[REG]], #0x1
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; CHECK-NEXT: and w0, [[REG2]], #0x1
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; CHECK: mov x[[REG:[0-9]+]], x0
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; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0x1
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; CHECK: and w0, [[REG2]], #0x1
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%conv = trunc i64 %a to i1
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ret i1 %conv
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}
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define zeroext i16 @i32_trunc_i16(i32 %a) nounwind ssp {
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entry:
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; CHECK-LABEL: i32_trunc_i16
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; CHECK: and [[REG:w[0-9]+]], w0, #0xffff
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; CHECK-NEXT: uxth w0, [[REG]]
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%conv = trunc i32 %a to i16
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ret i16 %conv
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}
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define zeroext i8 @i32_trunc_i8(i32 %a) nounwind ssp {
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entry:
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; CHECK-LABEL: i32_trunc_i8
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; CHECK: and [[REG:w[0-9]+]], w0, #0xff
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; CHECK-NEXT: uxtb w0, [[REG]]
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%conv = trunc i32 %a to i8
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ret i8 %conv
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}
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define zeroext i1 @i32_trunc_i1(i32 %a) nounwind ssp {
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entry:
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; CHECK-LABEL: i32_trunc_i1
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; CHECK: and [[REG:w[0-9]+]], w0, #0x1
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; CHECK-NEXT: and w0, [[REG]], #0x1
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%conv = trunc i32 %a to i1
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ret i1 %conv
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}
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define zeroext i8 @i16_trunc_i8(i16 zeroext %a) nounwind ssp {
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entry:
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; CHECK-LABEL: i16_trunc_i8
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; CHECK: and [[REG:w[0-9]+]], w0, #0xff
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; CHECK-NEXT: uxtb w0, [[REG]]
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%conv = trunc i16 %a to i8
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ret i8 %conv
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}
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define zeroext i1 @i16_trunc_i1(i16 zeroext %a) nounwind ssp {
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entry:
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; CHECK-LABEL: i16_trunc_i1
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; CHECK: and [[REG:w[0-9]+]], w0, #0x1
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; CHECK-NEXT: and w0, [[REG]], #0x1
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%conv = trunc i16 %a to i1
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ret i1 %conv
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}
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define zeroext i1 @i8_trunc_i1(i8 zeroext %a) nounwind ssp {
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entry:
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; CHECK-LABEL: i8_trunc_i1
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; CHECK: and [[REG:w[0-9]+]], w0, #0x1
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; CHECK-NEXT: and w0, [[REG]], #0x1
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%conv = trunc i8 %a to i1
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ret i1 %conv
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}
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; rdar://15101939
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define void @stack_trunc() nounwind {
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; CHECK-LABEL: stack_trunc
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@ -1,4 +1,4 @@
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; RUN: llc %s -o - -O2 -verify-machineinstrs -fast-isel=true | FileCheck %s
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; RUN: llc %s -o - -O0 -verify-machineinstrs -fast-isel=true | FileCheck %s
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "arm64-apple-ios8.0.0"
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@ -7,7 +7,7 @@ target triple = "arm64-apple-ios8.0.0"
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; This was incorrect as %.mux isn't available in the last bb.
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; CHECK: sxtw [[REG:x[0-9]+]]
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; CHECK: strh wzr, {{\[}}{{.*}}, [[REG]], lsl #1]
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; CHECK: strh wzr, {{\[}}[[REG]], {{.*}}, lsl #1]
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; Function Attrs: nounwind optsize ssp
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define void @EdgeLoop(i32 %dir, i32 %edge, i32 %width, i16* %tmp89, i32 %tmp136, i16 %tmp144) #0 {
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