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[Hexagon] Simplifying and formatting several patterns. Changing a pattern multiply to be expanded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228347 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
d04f83361d
commit
71166427a3
@ -1429,7 +1429,8 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
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setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
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setOperationAction(ISD::MULHS, MVT::i64, Expand);
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setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
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setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
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@ -4739,38 +4739,30 @@ def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
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// Map from a 64-bit select to an emulated 64-bit mux.
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// Hexagon does not support 64-bit MUXes; so emulate with combines.
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def : Pat <(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
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(i64 DoubleRegs:$src3)),
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(i64 (A2_combinew (i32 (C2_mux (i1 PredRegs:$src1),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
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subreg_hireg)),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
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subreg_hireg)))),
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(i32 (C2_mux (i1 PredRegs:$src1),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
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subreg_loreg)),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src3),
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subreg_loreg))))))>;
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def: Pat<(select (i1 PredRegs:$src1), (i64 DoubleRegs:$src2),
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(i64 DoubleRegs:$src3)),
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(A2_combinew (C2_mux PredRegs:$src1, (HiReg DoubleRegs:$src2),
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(HiReg DoubleRegs:$src3)),
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(C2_mux PredRegs:$src1, (LoReg DoubleRegs:$src2),
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(LoReg DoubleRegs:$src3)))>;
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// Map from a 1-bit select to logical ops.
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// From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3).
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def : Pat <(select (i1 PredRegs:$src1), (i1 PredRegs:$src2),
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(i1 PredRegs:$src3)),
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(C2_or (C2_and (i1 PredRegs:$src1), (i1 PredRegs:$src2)),
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(C2_and (C2_not (i1 PredRegs:$src1)), (i1 PredRegs:$src3)))>;
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def: Pat<(select (i1 PredRegs:$src1), (i1 PredRegs:$src2), (i1 PredRegs:$src3)),
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(C2_or (C2_and PredRegs:$src1, PredRegs:$src2),
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(C2_and (C2_not PredRegs:$src1), PredRegs:$src3))>;
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// Map Pd = load(addr) -> Rs = load(addr); Pd = Rs.
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def : Pat<(i1 (load ADDRriS11_2:$addr)),
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(i1 (C2_tfrrp (i32 (L2_loadrb_io AddrFI:$addr, 0))))>;
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// Map for truncating from 64 immediates to 32 bit immediates.
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def : Pat<(i32 (trunc (i64 DoubleRegs:$src))),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src), subreg_loreg))>;
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def: Pat<(i32 (trunc (i64 DoubleRegs:$src))),
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(LoReg DoubleRegs:$src)>;
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// Map for truncating from i64 immediates to i1 bit immediates.
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def : Pat<(i1 (trunc (i64 DoubleRegs:$src))),
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(i1 (C2_tfrrp (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src),
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subreg_loreg))))>;
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def: Pat<(i1 (trunc (i64 DoubleRegs:$src))),
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(C2_tfrrp (LoReg DoubleRegs:$src))>;
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// Map memb(Rs) = Rdd -> memb(Rs) = Rt.
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def : Pat<(truncstorei8 (i64 DoubleRegs:$src), ADDRriS11_0:$addr),
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@ -4804,30 +4796,25 @@ def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
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def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
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(S2_storerb_io AddrFI:$addr, 0, (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0)) )>;
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// Map Rdd = anyext(Rs) -> Rdd = A2_sxtw(Rs).
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// Hexagon_TODO: We can probably use combine but that will cost 2 instructions.
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// Better way to do this?
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def : Pat<(i64 (anyext (i32 IntRegs:$src1))),
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(i64 (A2_sxtw (i32 IntRegs:$src1)))>;
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// Map cmple -> cmpgt.
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// rs <= rt -> !(rs > rt).
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def : Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
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(i1 (C2_not (C2_cmpgti (i32 IntRegs:$src1), s10ExtPred:$src2)))>;
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let AddedComplexity = 30 in
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def: Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
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(C2_not (C2_cmpgti IntRegs:$src1, s10ExtPred:$src2))>;
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// rs <= rt -> !(rs > rt).
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def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
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(i1 (C2_not (C2_cmpgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))>;
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// Rss <= Rtt -> !(Rss > Rtt).
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def : Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
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(i1 (C2_not (C2_cmpgtp (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
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def: Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
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(C2_not (C2_cmpgtp DoubleRegs:$src1, DoubleRegs:$src2))>;
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// Map cmpne -> cmpeq.
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// Hexagon_TODO: We should improve on this.
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// rs != rt -> !(rs == rt).
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def : Pat <(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
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(i1 (C2_not(i1 (C2_cmpeqi (i32 IntRegs:$src1), s10ExtPred:$src2))))>;
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let AddedComplexity = 30 in
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def: Pat<(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
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(C2_not (C2_cmpeqi IntRegs:$src1, s10ExtPred:$src2))>;
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// Map cmpne(Rs) -> !cmpeqe(Rs).
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// rs != rt -> !(rs == rt).
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@ -4835,14 +4822,13 @@ def : Pat <(i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
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(i1 (C2_not (i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)))))>;
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// Convert setne back to xor for hexagon since we compute w/ pred registers.
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def : Pat <(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
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(i1 (C2_xor (i1 PredRegs:$src1), (i1 PredRegs:$src2)))>;
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def: Pat<(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
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(C2_xor PredRegs:$src1, PredRegs:$src2)>;
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// Map cmpne(Rss) -> !cmpew(Rss).
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// rs != rt -> !(rs == rt).
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def : Pat <(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
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(i1 (C2_not (i1 (C2_cmpeqp (i64 DoubleRegs:$src1),
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(i64 DoubleRegs:$src2)))))>;
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def: Pat<(i1 (setne (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
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(C2_not (C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2))>;
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// Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt).
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// rs >= rt -> !(rt > rs).
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@ -4850,20 +4836,21 @@ def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
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(i1 (C2_not (i1 (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)))))>;
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// cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
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def : Pat <(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)),
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(i1 (C2_cmpgti (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
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let AddedComplexity = 30 in
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def: Pat<(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)),
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(C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s8ExtPred:$src2))>;
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// Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
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// rss >= rtt -> !(rtt > rss).
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def : Pat <(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
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(i1 (C2_not (i1 (C2_cmpgtp (i64 DoubleRegs:$src2),
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(i64 DoubleRegs:$src1)))))>;
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def: Pat<(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
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(C2_not (C2_cmpgtp DoubleRegs:$src2, DoubleRegs:$src1))>;
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// Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm).
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// !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
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// rs < rt -> !(rs >= rt).
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def : Pat <(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
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(i1 (C2_not (C2_cmpgti (i32 IntRegs:$src1), (DEC_CONST_SIGNED s8ExtPred:$src2))))>;
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let AddedComplexity = 30 in
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def: Pat<(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
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(C2_not (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
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// Map cmplt(Rs, Rt) -> cmpgt(Rt, Rs).
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// rs < rt -> rt > rs.
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@ -4888,21 +4875,21 @@ def : Pat <(i1 (setult (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
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(i1 (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)))>;
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// Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs)
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def : Pat <(i1 (setuge (i32 IntRegs:$src1), 0)),
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(i1 (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src1)))>;
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def: Pat<(i1 (setuge (i32 IntRegs:$src1), 0)),
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(C2_cmpeq IntRegs:$src1, IntRegs:$src1)>;
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// Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1)
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def : Pat <(i1 (setuge (i32 IntRegs:$src1), u8ExtPred:$src2)),
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(i1 (C2_cmpgtui (i32 IntRegs:$src1), (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
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def: Pat<(i1 (setuge (i32 IntRegs:$src1), u8ExtPred:$src2)),
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(C2_cmpgtui IntRegs:$src1, (DEC_CONST_UNSIGNED u8ExtPred:$src2))>;
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// Generate cmpgtu(Rs, #u9)
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def : Pat <(i1 (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)),
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(i1 (C2_cmpgtui (i32 IntRegs:$src1), u9ExtPred:$src2))>;
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def: Pat<(i1 (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)),
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(C2_cmpgtui IntRegs:$src1, u9ExtPred:$src2)>;
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// Map from Rs >= Rt -> !(Rt > Rs).
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// rs >= rt -> !(rt > rs).
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def : Pat <(i1 (setuge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
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(i1 (C2_not (C2_cmpgtu (i32 IntRegs:$src2), (i32 IntRegs:$src1))))>;
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def: Pat<(i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
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(C2_not (C2_cmpgtup DoubleRegs:$src2, DoubleRegs:$src1))>;
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// Map from Rs >= Rt -> !(Rt > Rs).
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// rs >= rt -> !(rt > rs).
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@ -4916,17 +4903,17 @@ def : Pat <(i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
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// Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1).
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// Map from (Rs <= Rt) -> !(Rs > Rt).
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def : Pat <(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
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(i1 (C2_not (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))))>;
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def: Pat<(i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
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(C2_not (C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2))>;
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// Sign extends.
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// i1 -> i32
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def : Pat <(i32 (sext (i1 PredRegs:$src1))),
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(i32 (C2_muxii (i1 PredRegs:$src1), -1, 0))>;
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def: Pat<(i32 (sext (i1 PredRegs:$src1))),
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(C2_muxii PredRegs:$src1, -1, 0)>;
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// i1 -> i64
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def : Pat <(i64 (sext (i1 PredRegs:$src1))),
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(i64 (A2_combinew (A2_tfrsi -1), (C2_muxii (i1 PredRegs:$src1), -1, 0)))>;
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def: Pat<(i64 (sext (i1 PredRegs:$src1))),
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(A2_combinew (A2_tfrsi -1), (C2_muxii PredRegs:$src1, -1, 0))>;
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// Convert sign-extended load back to load and sign extend.
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// i8 -> i64
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@ -4948,11 +4935,10 @@ def: Pat <(i64 (sextloadi16 ADDRriS11_1:$src1)),
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def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
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(i64 (A2_sxtw (L2_loadri_io AddrFI:$src1, 0)))>;
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// Zero extends.
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// i1 -> i32
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def : Pat <(i32 (zext (i1 PredRegs:$src1))),
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(i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
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def: Pat<(i32 (zext (i1 PredRegs:$src1))),
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(C2_muxii PredRegs:$src1, 1, 0)>;
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// i1 -> i64
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def : Pat <(i64 (zext (i1 PredRegs:$src1))),
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@ -5016,12 +5002,12 @@ def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),
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(i32 (L2_loadri_io AddrFI:$src1, 0))>;
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// Map from Rs = Pd to Pd = mux(Pd, #1, #0)
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def : Pat <(i32 (zext (i1 PredRegs:$src1))),
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(i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
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def: Pat<(i32 (anyext (i1 PredRegs:$src1))),
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(C2_muxii PredRegs:$src1, 1, 0)>;
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// Map from Rs = Pd to Pd = mux(Pd, #1, #0)
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def : Pat <(i32 (anyext (i1 PredRegs:$src1))),
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(i32 (C2_muxii (i1 PredRegs:$src1), 1, 0))>;
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// Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0))
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def: Pat<(i64 (anyext (i1 PredRegs:$src1))),
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(A2_sxtw (C2_muxii PredRegs:$src1, 1, 0))>;
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// Map from Rss = Pd to Rdd = A2_sxtw (mux(Pd, #1, #0))
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def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
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@ -5111,91 +5097,38 @@ def : Pat<(i64 (zext (i32 IntRegs:$src1))),
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// Multiply 64-bit unsigned and use upper result.
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def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
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(i64
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(M2_dpmpyuu_acc_s0
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(i64
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(A2_combinew
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(A2_tfrsi 0),
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(i32
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(EXTRACT_SUBREG
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(i64
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(S2_lsr_i_p
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(i64
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(M2_dpmpyuu_acc_s0
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(i64
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(M2_dpmpyuu_acc_s0
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(i64
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(A2_combinew (A2_tfrsi 0),
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(i32
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(EXTRACT_SUBREG
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(i64
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(S2_lsr_i_p
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(i64
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(M2_dpmpyuu_s0
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
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subreg_loreg)),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
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subreg_loreg)))), 32)),
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subreg_loreg)))),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
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32)), subreg_loreg)))),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
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// Multiply 64-bit signed and use upper result.
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def : Pat <(mulhs (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
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(i64
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(M2_dpmpyss_acc_s0
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(i64
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(A2_combinew (A2_tfrsi 0),
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(i32
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(EXTRACT_SUBREG
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(i64
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(S2_lsr_i_p
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(i64
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(M2_dpmpyss_acc_s0
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(i64
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(M2_dpmpyss_acc_s0
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(i64
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(A2_combinew (A2_tfrsi 0),
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(i32
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(EXTRACT_SUBREG
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(i64
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(S2_lsr_i_p
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(i64
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(M2_dpmpyuu_s0
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
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subreg_loreg)),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
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subreg_loreg)))), 32)),
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subreg_loreg)))),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)))),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg)))),
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32)), subreg_loreg)))),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg)),
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(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))))>;
|
||||
(A2_addp
|
||||
(M2_dpmpyuu_acc_s0
|
||||
(S2_lsr_i_p
|
||||
(A2_addp
|
||||
(M2_dpmpyuu_acc_s0
|
||||
(S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $src1), (LoReg $src2)), 32),
|
||||
(HiReg $src1),
|
||||
(LoReg $src2)),
|
||||
(A2_combinew (A2_tfrsi 0),
|
||||
(LoReg (M2_dpmpyuu_s0 (LoReg $src1), (HiReg $src2))))),
|
||||
32),
|
||||
(HiReg $src1),
|
||||
(HiReg $src2)),
|
||||
(S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $src1), (HiReg $src2)), 32)
|
||||
)>;
|
||||
|
||||
// Hexagon specific ISD nodes.
|
||||
def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
|
||||
[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
|
||||
def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
|
||||
SDTCisVT<1, i32>]>;
|
||||
def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
|
||||
|
||||
def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
|
||||
SDTHexagonADJDYNALLOC>;
|
||||
// Needed to tag these instructions for stack layout.
|
||||
let usesCustomInserter = 1, isAsmParserOnly = 1 in
|
||||
def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
|
||||
s16Imm:$src2),
|
||||
"$dst = add($src1, #$src2)",
|
||||
[(set (i32 IntRegs:$dst),
|
||||
(Hexagon_ADJDYNALLOC (i32 IntRegs:$src1),
|
||||
s16ImmPred:$src2))]>;
|
||||
def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
|
||||
|
||||
// Needed to tag these instructions for stack layout.
|
||||
let isCodeGenOnly = 1, usesCustomInserter = 1 in
|
||||
def ADJDYNALLOC : T_Addri<s6Imm>;
|
||||
|
||||
def: Pat<(Hexagon_ADJDYNALLOC I32:$Rs, s16ImmPred:$s16),
|
||||
(ADJDYNALLOC I32:$Rs, imm:$s16)>;
|
||||
|
||||
def SDTHexagonARGEXTEND : SDTypeProfile<1, 1, [SDTCisVT<0, i32>]>;
|
||||
def Hexagon_ARGEXTEND : SDNode<"HexagonISD::ARGEXTEND", SDTHexagonARGEXTEND>;
|
||||
let isCodeGenOnly = 1 in
|
||||
def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
|
||||
"$dst = $src1",
|
||||
@ -5203,8 +5136,8 @@ def ARGEXTEND : ALU32_rr <(outs IntRegs:$dst), (ins IntRegs:$src1),
|
||||
(Hexagon_ARGEXTEND (i32 IntRegs:$src1)))]>;
|
||||
|
||||
let AddedComplexity = 100 in
|
||||
def : Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
|
||||
(COPY (i32 IntRegs:$src1))>;
|
||||
def: Pat<(i32 (sext_inreg (Hexagon_ARGEXTEND (i32 IntRegs:$src1)), i16)),
|
||||
(i32 IntRegs:$src1)>;
|
||||
|
||||
def HexagonWrapperJT: SDNode<"HexagonISD::WrapperJT", SDTIntUnaryOp>;
|
||||
|
||||
@ -5712,6 +5645,10 @@ let hasNewValue = 1 in {
|
||||
def S2_extractu : T_S2op_extract <"extractu", 0b1101, IntRegs, u5Imm>;
|
||||
}
|
||||
|
||||
// Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
|
||||
def: Pat<(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
|
||||
(M2_mpysin IntRegs:$src1, u8ImmPred:$src2)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// :raw for of tableindx[bdhw] insns
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -5743,10 +5680,6 @@ def S2_tableidxh : tableidxRaw<"tableidxh", 0b01>;
|
||||
def S2_tableidxw : tableidxRaw<"tableidxw", 0b10>;
|
||||
def S2_tableidxd : tableidxRaw<"tableidxd", 0b11>;
|
||||
|
||||
// Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
|
||||
def : Pat <(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
|
||||
(i32 (M2_mpysin (i32 IntRegs:$src1), u8ImmPred:$src2))>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// V3 Instructions +
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
; Check that we generate compare to predicate register.
|
||||
|
||||
define i32 @compare1(i32 %a, i32 %b) nounwind {
|
||||
; CHECK: p{{[0-3]}}{{ *}}={{ *}}!cmp.eq(r{{[0-9]+}},{{ *}}r{{[0-9]+}})
|
||||
; CHECK: p{{[0-3]}}{{ *}}={{ *[!]?}}cmp.eq(r{{[0-9]+}},{{ *}}r{{[0-9]+}})
|
||||
entry:
|
||||
%cmp = icmp ne i32 %a, %b
|
||||
%add = add nsw i32 %a, %b
|
||||
@ -12,7 +12,7 @@ entry:
|
||||
}
|
||||
|
||||
define i32 @compare2(i32 %a) nounwind {
|
||||
; CHECK: p{{[0-3]}}{{ *}}={{ *}}!cmp.eq(r{{[0-9]+}},{{ *}}#10)
|
||||
; CHECK: p{{[0-3]}}{{ *}}={{ *[!]?}}cmp.eq(r{{[0-9]+}},{{ *}}#10)
|
||||
entry:
|
||||
%cmp = icmp ne i32 %a, 10
|
||||
%add = add nsw i32 %a, 10
|
||||
|
||||
Loading…
Reference in New Issue
Block a user