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[WebAssembly] Check in an initial CFG Stackifier pass
This pass implements a simple algorithm for conversion from CFG to wasm's structured control flow. It doesn't yet handle multiple-entry loops; that will be added in a future patch. It also adds initial support for switch statements. Differential Revision: http://reviews.llvm.org/D12735 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247818 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
parent
39490133e4
commit
7146e900e8
@ -12,6 +12,7 @@ add_public_tablegen_target(WebAssemblyCommonTableGen)
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add_llvm_target(WebAssemblyCodeGen
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Relooper.cpp
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WebAssemblyAsmPrinter.cpp
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WebAssemblyCFGStackify.cpp
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WebAssemblyFastISel.cpp
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WebAssemblyFrameLowering.cpp
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WebAssemblyISelDAGToDAG.cpp
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@ -26,6 +26,8 @@ class FunctionPass;
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FunctionPass *createWebAssemblyISelDag(WebAssemblyTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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FunctionPass *createWebAssemblyCFGStackify();
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} // end namespace llvm
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#endif
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@ -73,6 +73,7 @@ private:
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void EmitGlobalVariable(const GlobalVariable *GV) override;
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void EmitJumpTableInfo() override;
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void EmitConstantPool() override;
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void EmitFunctionEntryLabel() override;
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void EmitFunctionBodyStart() override;
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@ -213,6 +214,10 @@ void WebAssemblyAsmPrinter::EmitConstantPool() {
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"WebAssembly disables constant pools");
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}
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void WebAssemblyAsmPrinter::EmitJumpTableInfo() {
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// Nothing to do; jump tables are incorporated into the instruction stream.
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}
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void WebAssemblyAsmPrinter::EmitFunctionEntryLabel() {
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SmallString<128> Str;
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raw_svector_ostream OS(Str);
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@ -293,6 +298,9 @@ void WebAssemblyAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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case MachineOperand::MO_GlobalAddress: {
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OS << ' ' << toSymbol(MO.getGlobal()->getName());
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} break;
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case MachineOperand::MO_MachineBasicBlock: {
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OS << ' ' << toSymbol(MO.getMBB()->getSymbol()->getName());
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} break;
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}
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OS << ')';
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}
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278
lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
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278
lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
Normal file
@ -0,0 +1,278 @@
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//===-- WebAssemblyCFGStackify.cpp - CFG Stackification -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief This file implements a CFG stacking pass.
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///
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/// This pass reorders the blocks in a function to put them into a reverse
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/// post-order [0], with special care to keep the order as similar as possible
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/// to the original order, and to keep loops contiguous even in the case of
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/// split backedges.
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///
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/// Then, it inserts BLOCK and LOOP markers to mark the start of scopes, since
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/// scope boundaries serve as the labels for WebAssembly's control transfers.
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///
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/// This is sufficient to convert arbitrary CFGs into a form that works on
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/// WebAssembly, provided that all loops are single-entry.
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///
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/// [0] https://en.wikipedia.org/wiki/Depth-first_search#Vertex_orderings
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssembly.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssemblySubtarget.h"
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#include "llvm/ADT/SCCIterator.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-cfg-stackify"
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namespace {
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class WebAssemblyCFGStackify final : public MachineFunctionPass {
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const char *getPassName() const override {
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return "WebAssembly CFG Stackify";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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public:
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static char ID; // Pass identification, replacement for typeid
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WebAssemblyCFGStackify() : MachineFunctionPass(ID) {}
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};
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} // end anonymous namespace
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char WebAssemblyCFGStackify::ID = 0;
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FunctionPass *llvm::createWebAssemblyCFGStackify() {
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return new WebAssemblyCFGStackify();
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}
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static void EliminateMultipleEntryLoops(MachineFunction &MF,
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const MachineLoopInfo &MLI) {
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SmallPtrSet<MachineBasicBlock *, 8> InSet;
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for (scc_iterator<MachineFunction *> I = scc_begin(&MF), E = scc_end(&MF);
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I != E; ++I) {
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const std::vector<MachineBasicBlock *> &CurrentSCC = *I;
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// Skip trivial SCCs.
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if (CurrentSCC.size() == 1)
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continue;
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InSet.insert(CurrentSCC.begin(), CurrentSCC.end());
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MachineBasicBlock *Header = nullptr;
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for (MachineBasicBlock *MBB : CurrentSCC) {
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for (MachineBasicBlock *Pred : MBB->predecessors()) {
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if (InSet.count(Pred))
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continue;
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if (!Header) {
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Header = MBB;
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break;
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}
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// TODO: Implement multiple-entry loops.
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report_fatal_error("multiple-entry loops are not supported yet");
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}
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}
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assert(MLI.isLoopHeader(Header));
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InSet.clear();
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}
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}
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namespace {
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/// Post-order traversal stack entry.
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struct POStackEntry {
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MachineBasicBlock *MBB;
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SmallVector<MachineBasicBlock *, 0> Succs;
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POStackEntry(MachineBasicBlock *MBB, MachineFunction &MF,
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const MachineLoopInfo &MLI);
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};
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} // end anonymous namespace
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POStackEntry::POStackEntry(MachineBasicBlock *MBB, MachineFunction &MF,
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const MachineLoopInfo &MLI)
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: MBB(MBB), Succs(MBB->successors()) {
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// RPO is not a unique form, since at every basic block with multiple
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// successors, the DFS has to pick which order to visit the successors in.
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// Sort them strategically (see below).
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MachineLoop *Loop = MLI.getLoopFor(MBB);
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MachineFunction::iterator Next = next(MachineFunction::iterator(MBB));
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MachineBasicBlock *LayoutSucc = Next == MF.end() ? nullptr : &*Next;
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std::stable_sort(
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Succs.begin(), Succs.end(),
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[=, &MLI](const MachineBasicBlock *A, const MachineBasicBlock *B) {
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if (A == B)
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return false;
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// Keep loops contiguous by preferring the block that's in the same
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// loop.
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MachineLoop *LoopA = MLI.getLoopFor(A);
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MachineLoop *LoopB = MLI.getLoopFor(B);
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if (LoopA == Loop && LoopB != Loop)
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return true;
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if (LoopA != Loop && LoopB == Loop)
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return false;
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// Minimize perturbation by preferring the block which is the immediate
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// layout successor.
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if (A == LayoutSucc)
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return true;
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if (B == LayoutSucc)
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return false;
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// TODO: More sophisticated orderings may be profitable here.
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return false;
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});
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}
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/// Sort the blocks in RPO, taking special care to make sure that loops are
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/// contiguous even in the case of split backedges.
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static void SortBlocks(MachineFunction &MF, const MachineLoopInfo &MLI) {
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// Note that we do our own RPO rather than using
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// "llvm/ADT/PostOrderIterator.h" because we want control over the order that
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// successors are visited in (see above). Also, we can sort the blocks in the
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// MachineFunction as we go.
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SmallPtrSet<MachineBasicBlock *, 16> Visited;
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SmallVector<POStackEntry, 16> Stack;
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MachineBasicBlock *Entry = MF.begin();
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Visited.insert(Entry);
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Stack.push_back(POStackEntry(Entry, MF, MLI));
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for (;;) {
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POStackEntry &Entry = Stack.back();
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SmallVectorImpl<MachineBasicBlock *> &Succs = Entry.Succs;
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if (!Succs.empty()) {
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MachineBasicBlock *Succ = Succs.pop_back_val();
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if (Visited.insert(Succ).second)
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Stack.push_back(POStackEntry(Succ, MF, MLI));
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continue;
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}
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// Put the block in its position in the MachineFunction.
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MachineBasicBlock &MBB = *Entry.MBB;
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MBB.moveBefore(MF.begin());
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// Branch instructions may utilize a fallthrough, so update them if a
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// fallthrough has been added or removed.
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if (!MBB.empty() && MBB.back().isTerminator() && !MBB.back().isBranch() &&
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!MBB.back().isBarrier())
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report_fatal_error(
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"Non-branch terminator with fallthrough cannot yet be rewritten");
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if (MBB.empty() || !MBB.back().isTerminator() || MBB.back().isBranch())
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MBB.updateTerminator();
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Stack.pop_back();
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if (Stack.empty())
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break;
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}
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// Now that we've sorted the blocks in RPO, renumber them.
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MF.RenumberBlocks();
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#ifndef NDEBUG
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for (auto &MBB : MF)
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if (MachineLoop *Loop = MLI.getLoopFor(&MBB)) {
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// Assert that loops are contiguous.
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assert(Loop->getHeader() == Loop->getTopBlock());
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assert(Loop->getHeader() == &MBB ||
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MLI.getLoopFor(prev(MachineFunction::iterator(&MBB))) == Loop);
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} else {
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// Assert that non-loops have no backedge predecessors.
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for (auto Pred : MBB.predecessors())
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assert(Pred->getNumber() < MBB.getNumber() &&
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"CFG still has multiple-entry loops");
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}
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#endif
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}
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/// Insert BLOCK markers at appropriate places.
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static void PlaceBlockMarkers(MachineBasicBlock &MBB, MachineBasicBlock &Succ,
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MachineFunction &MF, const MachineLoopInfo &MLI,
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const WebAssemblyInstrInfo &TII) {
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// Backward branches are loop backedges, and we place the LOOP markers
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// separately. So only consider forward branches here.
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if (Succ.getNumber() <= MBB.getNumber())
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return;
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// Place the BLOCK for a forward branch. For simplicity, we just insert
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// blocks immediately inside loop boundaries.
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MachineLoop *Loop = MLI.getLoopFor(&Succ);
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MachineBasicBlock &Header = *(Loop ? Loop->getHeader() : &MF.front());
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MachineBasicBlock::iterator InsertPos = Header.begin(), End = Header.end();
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if (InsertPos != End) {
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if (InsertPos->getOpcode() == WebAssembly::LOOP)
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++InsertPos;
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int SuccNumber = Succ.getNumber();
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// Position the BLOCK in nesting order.
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for (; InsertPos != End && InsertPos->getOpcode() == WebAssembly::BLOCK;
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++InsertPos) {
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int N = InsertPos->getOperand(0).getMBB()->getNumber();
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if (N < SuccNumber)
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break;
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// If there's already a BLOCK for Succ, we don't need another.
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if (N == SuccNumber)
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return;
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}
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}
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BuildMI(Header, InsertPos, DebugLoc(), TII.get(WebAssembly::BLOCK))
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.addMBB(&Succ);
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}
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/// Insert LOOP and BLOCK markers at appropriate places.
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static void PlaceMarkers(MachineFunction &MF, const MachineLoopInfo &MLI,
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const WebAssemblyInstrInfo &TII) {
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for (auto &MBB : MF) {
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// Place the LOOP for loops.
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if (MachineLoop *Loop = MLI.getLoopFor(&MBB))
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if (Loop->getHeader() == &MBB)
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BuildMI(MBB, MBB.begin(), DebugLoc(), TII.get(WebAssembly::LOOP))
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.addMBB(Loop->getBottomBlock());
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// Check for forward branches and switches that need BLOCKS placed.
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for (auto &Term : MBB.terminators())
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for (auto &MO : Term.operands())
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if (MO.isMBB())
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PlaceBlockMarkers(MBB, *MO.getMBB(), MF, MLI, TII);
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}
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}
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bool WebAssemblyCFGStackify::runOnMachineFunction(MachineFunction &MF) {
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DEBUG(dbgs() << "********** CFG Stackifying **********\n"
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"********** Function: "
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<< MF.getName() << '\n');
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const auto &MLI = getAnalysis<MachineLoopInfo>();
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const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
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// RPO sorting needs all loops to be single-entry.
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EliminateMultipleEntryLoops(MF, MLI);
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// Sort the blocks in RPO, with contiguous loops.
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SortBlocks(MF, MLI);
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// Place the BLOCK and LOOP markers to indicate the beginnings of scopes.
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PlaceMarkers(MF, MLI, TII);
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return true;
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}
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@ -19,5 +19,7 @@ HANDLE_NODETYPE(CALL0)
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HANDLE_NODETYPE(RETURN)
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HANDLE_NODETYPE(ARGUMENT)
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HANDLE_NODETYPE(Wrapper)
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HANDLE_NODETYPE(BRIF)
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HANDLE_NODETYPE(SWITCH)
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// add memory opcodes starting at ISD::FIRST_TARGET_MEMORY_OPCODE here...
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@ -20,6 +20,7 @@
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#include "WebAssemblyTargetObjectFile.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/IR/DiagnosticInfo.h"
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@ -114,6 +115,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
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computeRegisterProperties(Subtarget->getRegisterInfo());
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setOperationAction(ISD::GlobalAddress, MVTPtr, Custom);
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setOperationAction(ISD::JumpTable, MVTPtr, Custom);
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for (auto T : {MVT::f32, MVT::f64}) {
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// Don't expand the floating-point types to constant pools.
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@ -153,6 +155,14 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVTPtr, Expand);
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// Expand these forms; we pattern-match the forms that we can handle in isel.
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for (auto T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64})
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for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
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setOperationAction(Op, T, Expand);
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// We have custom switch handling.
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setOperationAction(ISD::BR_JT, MVT::Other, Custom);
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// WebAssembly doesn't have:
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// - Floating-point extending loads.
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// - Floating-point truncating stores.
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@ -365,6 +375,10 @@ SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op,
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return SDValue();
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case ISD::GlobalAddress:
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return LowerGlobalAddress(Op, DAG);
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case ISD::JumpTable:
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return LowerJumpTable(Op, DAG);
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case ISD::BR_JT:
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return LowerBR_JT(Op, DAG);
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}
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}
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@ -382,6 +396,43 @@ SDValue WebAssemblyTargetLowering::LowerGlobalAddress(SDValue Op,
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DAG.getTargetGlobalAddress(GA->getGlobal(), DL, VT));
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}
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SDValue WebAssemblyTargetLowering::LowerJumpTable(SDValue Op,
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SelectionDAG &DAG) const {
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// There's no need for a Wrapper node because we always incorporate a jump
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// table operand into a SWITCH instruction, rather than ever materializing
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// it in a register.
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const JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
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return DAG.getTargetJumpTable(JT->getIndex(), Op.getValueType(),
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JT->getTargetFlags());
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}
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SDValue WebAssemblyTargetLowering::LowerBR_JT(SDValue Op,
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SelectionDAG &DAG) const {
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SDLoc DL(Op);
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SDValue Chain = Op.getOperand(0);
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const auto *JT = cast<JumpTableSDNode>(Op.getOperand(1));
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SDValue Index = Op.getOperand(2);
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assert(JT->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
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SmallVector<SDValue, 8> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Index);
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MachineJumpTableInfo *MJTI = DAG.getMachineFunction().getJumpTableInfo();
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const auto &MBBs = MJTI->getJumpTables()[JT->getIndex()].MBBs;
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// TODO: For now, we just pick something arbitrary for a default case for now.
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// We really want to sniff out the guard and put in the real default case (and
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// delete the guard).
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Ops.push_back(DAG.getBasicBlock(MBBs[0]));
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// Add an operand for each case.
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for (auto MBB : MBBs)
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Ops.push_back(DAG.getBasicBlock(MBB));
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return DAG.getNode(WebAssemblyISD::SWITCH, DL, MVT::Other, Ops);
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}
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//===----------------------------------------------------------------------===//
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// WebAssembly Optimization Hooks
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//===----------------------------------------------------------------------===//
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@ -69,6 +69,8 @@ private:
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// Custom lowering hooks.
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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};
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namespace WebAssembly {
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@ -25,6 +25,29 @@
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* switch: switch statement with fallthrough
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*/
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let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
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def BRIF : I<(outs), (ins bb_op:$dst, Int32:$a),
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[(brcond Int32:$a, bb:$dst)]>;
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let isBarrier = 1 in {
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def BR : I<(outs), (ins bb_op:$dst),
|
||||
[(br bb:$dst)]>;
|
||||
} // isBarrier = 1
|
||||
} // isBranch = 1, isTerminator = 1, hasCtrlDep = 1
|
||||
|
||||
// TODO: SelectionDAG's lowering insists on using a pointer as the index for
|
||||
// jump tables, so in practice we don't ever use SWITCH_I64 in wasm32 mode
|
||||
// currently.
|
||||
let isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
|
||||
def SWITCH_I32 : I<(outs), (ins Int32:$index, variable_ops),
|
||||
[(WebAssemblyswitch Int32:$index)]>;
|
||||
def SWITCH_I64 : I<(outs), (ins Int64:$index, variable_ops),
|
||||
[(WebAssemblyswitch Int64:$index)]>;
|
||||
} // isTerminator = 1, hasCtrlDep = 1, isBarrier = 1
|
||||
|
||||
// Placemarkers to indicate the start of a block or loop scope.
|
||||
def BLOCK : I<(outs), (ins bb_op:$dst), []>;
|
||||
def LOOP : I<(outs), (ins bb_op:$dst), []>;
|
||||
|
||||
multiclass RETURN<WebAssemblyRegClass vt> {
|
||||
def RETURN_#vt : I<(outs), (ins vt:$val), [(WebAssemblyreturn vt:$val)]>;
|
||||
}
|
||||
|
||||
@ -37,3 +37,89 @@ void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
|
||||
BuildMI(MBB, I, DL, get(WebAssembly::COPY), DestReg)
|
||||
.addReg(SrcReg, KillSrc ? RegState::Kill : 0);
|
||||
}
|
||||
|
||||
// Branch analysis.
|
||||
bool WebAssemblyInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock *&TBB,
|
||||
MachineBasicBlock *&FBB,
|
||||
SmallVectorImpl<MachineOperand> &Cond,
|
||||
bool AllowModify) const {
|
||||
bool HaveCond = false;
|
||||
for (MachineInstr &MI : iterator_range<MachineBasicBlock::instr_iterator>(
|
||||
MBB.getFirstInstrTerminator(), MBB.instr_end())) {
|
||||
switch (MI.getOpcode()) {
|
||||
default:
|
||||
// Unhandled instruction; bail out.
|
||||
return true;
|
||||
case WebAssembly::BRIF:
|
||||
if (HaveCond)
|
||||
return true;
|
||||
Cond.push_back(MI.getOperand(1));
|
||||
TBB = MI.getOperand(0).getMBB();
|
||||
HaveCond = true;
|
||||
break;
|
||||
case WebAssembly::BR:
|
||||
if (!HaveCond)
|
||||
TBB = MI.getOperand(0).getMBB();
|
||||
else
|
||||
FBB = MI.getOperand(0).getMBB();
|
||||
break;
|
||||
}
|
||||
if (MI.isBarrier())
|
||||
break;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
unsigned WebAssemblyInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
|
||||
MachineBasicBlock::instr_iterator I = MBB.instr_end();
|
||||
unsigned Count = 0;
|
||||
|
||||
while (I != MBB.instr_begin()) {
|
||||
--I;
|
||||
if (I->isDebugValue())
|
||||
continue;
|
||||
if (!I->isTerminator())
|
||||
break;
|
||||
// Remove the branch.
|
||||
I->eraseFromParent();
|
||||
I = MBB.instr_end();
|
||||
++Count;
|
||||
}
|
||||
|
||||
return Count;
|
||||
}
|
||||
|
||||
unsigned WebAssemblyInstrInfo::InsertBranch(
|
||||
MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
|
||||
ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
|
||||
assert(Cond.size() <= 1);
|
||||
|
||||
if (Cond.empty()) {
|
||||
if (!TBB)
|
||||
return 0;
|
||||
|
||||
BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
|
||||
return 1;
|
||||
}
|
||||
|
||||
BuildMI(&MBB, DL, get(WebAssembly::BRIF))
|
||||
.addMBB(TBB)
|
||||
.addOperand(Cond[0]);
|
||||
if (!FBB)
|
||||
return 1;
|
||||
|
||||
BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
|
||||
return 2;
|
||||
}
|
||||
|
||||
bool WebAssemblyInstrInfo::ReverseBranchCondition(
|
||||
SmallVectorImpl<MachineOperand> &Cond) const {
|
||||
assert(Cond.size() == 1);
|
||||
|
||||
// TODO: Add branch reversal here... And re-enable MachineBlockPlacementID
|
||||
// when we do.
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
@ -37,6 +37,18 @@ public:
|
||||
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
||||
DebugLoc DL, unsigned DestReg, unsigned SrcReg,
|
||||
bool KillSrc) const override;
|
||||
|
||||
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
|
||||
MachineBasicBlock *&FBB,
|
||||
SmallVectorImpl<MachineOperand> &Cond,
|
||||
bool AllowModify = false) const override;
|
||||
unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
|
||||
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
ArrayRef<MachineOperand> Cond,
|
||||
DebugLoc DL) const override;
|
||||
bool
|
||||
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
|
||||
};
|
||||
|
||||
} // end namespace llvm
|
||||
|
||||
@ -30,6 +30,7 @@ def SDT_WebAssemblyCallSeqEnd :
|
||||
SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
|
||||
def SDT_WebAssemblyCall0 : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
|
||||
def SDT_WebAssemblyCall1 : SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>;
|
||||
def SDT_WebAssemblySwitch : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
|
||||
def SDT_WebAssemblyArgument : SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>;
|
||||
def SDT_WebAssemblyReturn : SDTypeProfile<0, -1, []>;
|
||||
def SDT_WebAssemblyWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
|
||||
@ -51,6 +52,9 @@ def WebAssemblycall0 : SDNode<"WebAssemblyISD::CALL0",
|
||||
def WebAssemblycall1 : SDNode<"WebAssemblyISD::CALL1",
|
||||
SDT_WebAssemblyCall1,
|
||||
[SDNPHasChain, SDNPVariadic]>;
|
||||
def WebAssemblyswitch : SDNode<"WebAssemblyISD::SWITCH",
|
||||
SDT_WebAssemblySwitch,
|
||||
[SDNPHasChain, SDNPVariadic]>;
|
||||
def WebAssemblyargument : SDNode<"WebAssemblyISD::ARGUMENT",
|
||||
SDT_WebAssemblyArgument>;
|
||||
def WebAssemblyreturn : SDNode<"WebAssemblyISD::RETURN",
|
||||
@ -69,6 +73,8 @@ def WebAssemblywrapper : SDNode<"WebAssemblyISD::Wrapper",
|
||||
* set_local: set the current value of a local variable
|
||||
*/
|
||||
|
||||
def bb_op : Operand<OtherVT>;
|
||||
def tjumptable_op : Operand<iPTR>;
|
||||
def global : Operand<iPTR>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -96,9 +102,11 @@ def Immediate_F32 : I<(outs Float32:$res), (ins f32imm:$imm),
|
||||
def Immediate_F64 : I<(outs Float64:$res), (ins f64imm:$imm),
|
||||
[(set Float64:$res, fpimm:$imm)]>;
|
||||
|
||||
// Special types of immediates.
|
||||
// Special types of immediates. FIXME: Hard-coded as 32-bit for now.
|
||||
def GLOBAL : I<(outs Int32:$dst), (ins global:$addr),
|
||||
[(set Int32:$dst, (WebAssemblywrapper tglobaladdr:$addr))]>;
|
||||
def JUMP_TABLE : I<(outs Int32:$dst), (ins tjumptable_op:$addr),
|
||||
[(set Int32:$dst, (WebAssemblywrapper tjumptable:$addr))]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Additional sets of instructions.
|
||||
|
||||
@ -159,8 +159,14 @@ void WebAssemblyPassConfig::addPostRegAlloc() {
|
||||
disablePass(&PrologEpilogCodeInserterID);
|
||||
// Fails with: should be run after register allocation.
|
||||
disablePass(&MachineCopyPropagationID);
|
||||
|
||||
// TODO: Until we get ReverseBranchCondition support, MachineBlockPlacement
|
||||
// can create ugly-looking control flow.
|
||||
disablePass(&MachineBlockPlacementID);
|
||||
}
|
||||
|
||||
void WebAssemblyPassConfig::addPreSched2() {}
|
||||
|
||||
void WebAssemblyPassConfig::addPreEmitPass() {}
|
||||
void WebAssemblyPassConfig::addPreEmitPass() {
|
||||
addPass(createWebAssemblyCFGStackify());
|
||||
}
|
||||
|
||||
274
test/CodeGen/WebAssembly/cfg-stackify.ll
Normal file
274
test/CodeGen/WebAssembly/cfg-stackify.ll
Normal file
@ -0,0 +1,274 @@
|
||||
; RUN: llc < %s -asm-verbose=false | FileCheck %s
|
||||
|
||||
; Test the CFG stackifier pass.
|
||||
|
||||
target datalayout = "e-p:32:32-i64:64-n32:64-S128"
|
||||
target triple = "wasm32-unknown-unknown"
|
||||
|
||||
declare void @something()
|
||||
|
||||
; Test that loops are made contiguous, even in the presence of split backedges.
|
||||
|
||||
; CHECK-LABEL: test0
|
||||
; CHECK: (loop
|
||||
; CHECK: (add
|
||||
; CHECK: (brif
|
||||
; CHECK: (call
|
||||
; CHECK: (br $BB0_1)
|
||||
; CHECK: (return)
|
||||
define void @test0(i32 %n) {
|
||||
entry:
|
||||
br label %header
|
||||
|
||||
header:
|
||||
%i = phi i32 [ 0, %entry ], [ %i.next, %back ]
|
||||
%i.next = add i32 %i, 1
|
||||
|
||||
%c = icmp slt i32 %i.next, %n
|
||||
br i1 %c, label %back, label %exit
|
||||
|
||||
exit:
|
||||
ret void
|
||||
|
||||
back:
|
||||
call void @something()
|
||||
br label %header
|
||||
}
|
||||
|
||||
; Same as test0, but the branch condition is reversed.
|
||||
|
||||
; CHECK-LABEL: test1
|
||||
; CHECK: (loop
|
||||
; CHECK: (add
|
||||
; CHECK: (brif
|
||||
; CHECK: (call
|
||||
; CHECK: (br $BB1_1)
|
||||
; CHECK: (return)
|
||||
define void @test1(i32 %n) {
|
||||
entry:
|
||||
br label %header
|
||||
|
||||
header:
|
||||
%i = phi i32 [ 0, %entry ], [ %i.next, %back ]
|
||||
%i.next = add i32 %i, 1
|
||||
|
||||
%c = icmp sge i32 %i.next, %n
|
||||
br i1 %c, label %exit, label %back
|
||||
|
||||
exit:
|
||||
ret void
|
||||
|
||||
back:
|
||||
call void @something()
|
||||
br label %header
|
||||
}
|
||||
|
||||
; Test that a simple loop is handled as expected.
|
||||
|
||||
; CHECK-LABEL: test2
|
||||
; CHECK: (block $BB2_2)
|
||||
; CHECK: (brif $BB2_2 {{.*}})
|
||||
; CHECK: BB2_1:
|
||||
; CHECK: (brif $BB2_1 @14)
|
||||
; CHECK: BB2_2:
|
||||
; CHECK: (return)
|
||||
define void @test2(double* nocapture %p, i32 %n) {
|
||||
entry:
|
||||
%cmp.4 = icmp sgt i32 %n, 0
|
||||
br i1 %cmp.4, label %for.body.preheader, label %for.end
|
||||
|
||||
for.body.preheader:
|
||||
br label %for.body
|
||||
|
||||
for.body:
|
||||
%i.05 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ]
|
||||
%arrayidx = getelementptr inbounds double, double* %p, i32 %i.05
|
||||
%0 = load double, double* %arrayidx, align 8
|
||||
%mul = fmul double %0, 3.200000e+00
|
||||
store double %mul, double* %arrayidx, align 8
|
||||
%inc = add nuw nsw i32 %i.05, 1
|
||||
%exitcond = icmp eq i32 %inc, %n
|
||||
br i1 %exitcond, label %for.end.loopexit, label %for.body
|
||||
|
||||
for.end.loopexit:
|
||||
br label %for.end
|
||||
|
||||
for.end:
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: doublediamond
|
||||
; CHECK: (block $BB3_5)
|
||||
; CHECK: (block $BB3_4)
|
||||
; CHECK: (block $BB3_2)
|
||||
; CHECK: (brif $BB3_2 @4)
|
||||
; CHECK: (br $BB3_5)
|
||||
; CHECK: BB3_2:
|
||||
; CHECK: (brif $BB3_4 @7)
|
||||
; CHECK: (br $BB3_5)
|
||||
; CHECK: BB3_4:
|
||||
; CHECK: BB3_5:
|
||||
; CHECK: (return @3)
|
||||
define i32 @doublediamond(i32 %a, i32 %b, i32* %p) {
|
||||
entry:
|
||||
%c = icmp eq i32 %a, 0
|
||||
%d = icmp eq i32 %b, 0
|
||||
store volatile i32 0, i32* %p
|
||||
br i1 %c, label %true, label %false
|
||||
true:
|
||||
store volatile i32 1, i32* %p
|
||||
br label %exit
|
||||
false:
|
||||
store volatile i32 2, i32* %p
|
||||
br i1 %d, label %ft, label %ff
|
||||
ft:
|
||||
store volatile i32 3, i32* %p
|
||||
br label %exit
|
||||
ff:
|
||||
store volatile i32 4, i32* %p
|
||||
br label %exit
|
||||
exit:
|
||||
store volatile i32 5, i32* %p
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
; CHECK-LABEL: triangle
|
||||
; CHECK: (block $BB4_2)
|
||||
; CHECK: (brif $BB4_2 @3)
|
||||
; CHECK: BB4_2:
|
||||
; CHECK: (return @2)
|
||||
define i32 @triangle(i32* %p, i32 %a) {
|
||||
entry:
|
||||
%c = icmp eq i32 %a, 0
|
||||
store volatile i32 0, i32* %p
|
||||
br i1 %c, label %true, label %exit
|
||||
true:
|
||||
store volatile i32 1, i32* %p
|
||||
br label %exit
|
||||
exit:
|
||||
store volatile i32 2, i32* %p
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
; CHECK-LABEL: diamond
|
||||
; CHECK: (block $BB5_3)
|
||||
; CHECK: (block $BB5_2)
|
||||
; CHECK: (brif $BB5_2 @3)
|
||||
; CHECK: (br $BB5_3)
|
||||
; CHECK: BB5_2:
|
||||
; CHECK: BB5_3:
|
||||
; CHECK: (return @2)
|
||||
define i32 @diamond(i32* %p, i32 %a) {
|
||||
entry:
|
||||
%c = icmp eq i32 %a, 0
|
||||
store volatile i32 0, i32* %p
|
||||
br i1 %c, label %true, label %false
|
||||
true:
|
||||
store volatile i32 1, i32* %p
|
||||
br label %exit
|
||||
false:
|
||||
store volatile i32 2, i32* %p
|
||||
br label %exit
|
||||
exit:
|
||||
store volatile i32 3, i32* %p
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
; CHECK-LABEL: single_block
|
||||
; CHECK-NOT: br
|
||||
; CHECK: (return @1)
|
||||
define i32 @single_block(i32* %p) {
|
||||
entry:
|
||||
store volatile i32 0, i32* %p
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
; CHECK-LABEL: minimal_loop
|
||||
; CHECK-NOT: br
|
||||
; CHECK: BB7_1:
|
||||
; CHECK: (store_i32 @0 @2)
|
||||
; CHECK: (br $BB7_1)
|
||||
define i32 @minimal_loop(i32* %p) {
|
||||
entry:
|
||||
store volatile i32 0, i32* %p
|
||||
br label %loop
|
||||
loop:
|
||||
store volatile i32 1, i32* %p
|
||||
br label %loop
|
||||
}
|
||||
|
||||
; CHECK-LABEL: simple_loop
|
||||
; CHECK-NOT: br
|
||||
; CHECK: BB8_1:
|
||||
; CHECK: (loop $BB8_1)
|
||||
; CHECK: (brif $BB8_1 @4)
|
||||
; CHECK: (return @2)
|
||||
define i32 @simple_loop(i32* %p, i32 %a) {
|
||||
entry:
|
||||
%c = icmp eq i32 %a, 0
|
||||
store volatile i32 0, i32* %p
|
||||
br label %loop
|
||||
loop:
|
||||
store volatile i32 1, i32* %p
|
||||
br i1 %c, label %loop, label %exit
|
||||
exit:
|
||||
store volatile i32 2, i32* %p
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
; CHECK-LABEL: doubletriangle
|
||||
; CHECK: (block $BB9_4)
|
||||
; CHECK: (block $BB9_3)
|
||||
; CHECK: (brif $BB9_4 @4)
|
||||
; CHECK: (brif $BB9_3 @7)
|
||||
; CHECK: BB9_3:
|
||||
; CHECK: BB9_4:
|
||||
; CHECK: (return @3)
|
||||
define i32 @doubletriangle(i32 %a, i32 %b, i32* %p) {
|
||||
entry:
|
||||
%c = icmp eq i32 %a, 0
|
||||
%d = icmp eq i32 %b, 0
|
||||
store volatile i32 0, i32* %p
|
||||
br i1 %c, label %true, label %exit
|
||||
true:
|
||||
store volatile i32 2, i32* %p
|
||||
br i1 %d, label %tt, label %tf
|
||||
tt:
|
||||
store volatile i32 3, i32* %p
|
||||
br label %tf
|
||||
tf:
|
||||
store volatile i32 4, i32* %p
|
||||
br label %exit
|
||||
exit:
|
||||
store volatile i32 5, i32* %p
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
; CHECK-LABEL: ifelse_earlyexits
|
||||
; CHECK: (block $BB10_4)
|
||||
; CHECK: (block $BB10_2)
|
||||
; CHECK: (brif $BB10_2 @4)
|
||||
; CHECK: (br $BB10_4)
|
||||
; CHECK: BB10_2:
|
||||
; CHECK: (brif $BB10_4 @7)
|
||||
; CHECK: BB10_4:
|
||||
; CHECK: (return @3)
|
||||
define i32 @ifelse_earlyexits(i32 %a, i32 %b, i32* %p) {
|
||||
entry:
|
||||
%c = icmp eq i32 %a, 0
|
||||
%d = icmp eq i32 %b, 0
|
||||
store volatile i32 0, i32* %p
|
||||
br i1 %c, label %true, label %false
|
||||
true:
|
||||
store volatile i32 1, i32* %p
|
||||
br label %exit
|
||||
false:
|
||||
store volatile i32 2, i32* %p
|
||||
br i1 %d, label %ft, label %exit
|
||||
ft:
|
||||
store volatile i32 3, i32* %p
|
||||
br label %exit
|
||||
exit:
|
||||
store volatile i32 4, i32* %p
|
||||
ret i32 0
|
||||
}
|
||||
@ -1,8 +1,5 @@
|
||||
; RUN: llc < %s -asm-verbose=false | FileCheck %s
|
||||
|
||||
; This test depends on branching support, which is not yet checked in.
|
||||
; XFAIL: *
|
||||
|
||||
; Test that phis are lowered.
|
||||
|
||||
target datalayout = "e-p:32:32-i64:64-n32:64-S128"
|
||||
@ -29,7 +26,7 @@ done:
|
||||
; Swap phis.
|
||||
|
||||
; CHECK-LABEL: test1
|
||||
; CHECK: BB0_1:
|
||||
; CHECK: BB1_1:
|
||||
; CHECK: (setlocal [[REG0:@.*]] [[REG1:@.*]])
|
||||
; CHECK: (setlocal [[REG1]] [[REG2:@.*]])
|
||||
; CHECK: (setlocal [[REG2]] [[REG0]])
|
||||
|
||||
173
test/CodeGen/WebAssembly/switch.ll
Normal file
173
test/CodeGen/WebAssembly/switch.ll
Normal file
@ -0,0 +1,173 @@
|
||||
; RUN: llc < %s -asm-verbose=false | FileCheck %s
|
||||
|
||||
; Test switch instructions.
|
||||
|
||||
target datalayout = "e-p:32:32-i64:64-n32:64-S128"
|
||||
target triple = "wasm32-unknown-unknown"
|
||||
|
||||
declare void @foo0()
|
||||
declare void @foo1()
|
||||
declare void @foo2()
|
||||
declare void @foo3()
|
||||
declare void @foo4()
|
||||
declare void @foo5()
|
||||
|
||||
; CHECK-LABEL: bar32
|
||||
; CHECK: (block $BB0_8)
|
||||
; CHECK: (block $BB0_7)
|
||||
; CHECK: (block $BB0_6)
|
||||
; CHECK: (block $BB0_5)
|
||||
; CHECK: (block $BB0_4)
|
||||
; CHECK: (block $BB0_3)
|
||||
; CHECK: (block $BB0_2)
|
||||
; CHECK: (switch {{.*}} $BB0_2 $BB0_2 $BB0_2 $BB0_2 $BB0_2 $BB0_2 $BB0_2 $BB0_2 $BB0_3 $BB0_3 $BB0_3 $BB0_3 $BB0_3 $BB0_3 $BB0_3 $BB0_3 $BB0_4 $BB0_4 $BB0_4 $BB0_4 $BB0_4 $BB0_4 $BB0_5 $BB0_6 $BB0_7)
|
||||
; CHECk: BB0_2:
|
||||
; CHECK: (setlocal {{.*}} (global $foo0))
|
||||
; CHECK: BB0_3:
|
||||
; CHECK: (setlocal {{.*}} (global $foo1))
|
||||
; CHECK: BB0_4:
|
||||
; CHECK: (setlocal {{.*}} (global $foo2))
|
||||
; CHECK: BB0_5:
|
||||
; CHECK: (setlocal {{.*}} (global $foo3))
|
||||
; CHECK: BB0_6:
|
||||
; CHECK: (setlocal {{.*}} (global $foo4))
|
||||
; CHECK: BB0_7:
|
||||
; CHECK: (setlocal {{.*}} (global $foo5))
|
||||
; CHECK: BB0_8:
|
||||
; CHECK: (return)
|
||||
define void @bar32(i32 %n) {
|
||||
entry:
|
||||
switch i32 %n, label %sw.epilog [
|
||||
i32 0, label %sw.bb
|
||||
i32 1, label %sw.bb
|
||||
i32 2, label %sw.bb
|
||||
i32 3, label %sw.bb
|
||||
i32 4, label %sw.bb
|
||||
i32 5, label %sw.bb
|
||||
i32 6, label %sw.bb
|
||||
i32 7, label %sw.bb.1
|
||||
i32 8, label %sw.bb.1
|
||||
i32 9, label %sw.bb.1
|
||||
i32 10, label %sw.bb.1
|
||||
i32 11, label %sw.bb.1
|
||||
i32 12, label %sw.bb.1
|
||||
i32 13, label %sw.bb.1
|
||||
i32 14, label %sw.bb.1
|
||||
i32 15, label %sw.bb.2
|
||||
i32 16, label %sw.bb.2
|
||||
i32 17, label %sw.bb.2
|
||||
i32 18, label %sw.bb.2
|
||||
i32 19, label %sw.bb.2
|
||||
i32 20, label %sw.bb.2
|
||||
i32 21, label %sw.bb.3
|
||||
i32 22, label %sw.bb.4
|
||||
i32 23, label %sw.bb.5
|
||||
]
|
||||
|
||||
sw.bb: ; preds = %entry, %entry, %entry, %entry, %entry, %entry, %entry
|
||||
tail call void @foo0()
|
||||
br label %sw.epilog
|
||||
|
||||
sw.bb.1: ; preds = %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry
|
||||
tail call void @foo1()
|
||||
br label %sw.epilog
|
||||
|
||||
sw.bb.2: ; preds = %entry, %entry, %entry, %entry, %entry, %entry
|
||||
tail call void @foo2()
|
||||
br label %sw.epilog
|
||||
|
||||
sw.bb.3: ; preds = %entry
|
||||
tail call void @foo3()
|
||||
br label %sw.epilog
|
||||
|
||||
sw.bb.4: ; preds = %entry
|
||||
tail call void @foo4()
|
||||
br label %sw.epilog
|
||||
|
||||
sw.bb.5: ; preds = %entry
|
||||
tail call void @foo5()
|
||||
br label %sw.epilog
|
||||
|
||||
sw.epilog: ; preds = %entry, %sw.bb.5, %sw.bb.4, %sw.bb.3, %sw.bb.2, %sw.bb.1, %sw.bb
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: bar64
|
||||
; CHECK: (block $BB1_8)
|
||||
; CHECK: (block $BB1_7)
|
||||
; CHECK: (block $BB1_6)
|
||||
; CHECK: (block $BB1_5)
|
||||
; CHECK: (block $BB1_4)
|
||||
; CHECK: (block $BB1_3)
|
||||
; CHECK: (block $BB1_2)
|
||||
; CHECK: (switch {{.*}} $BB1_2 $BB1_2 $BB1_2 $BB1_2 $BB1_2 $BB1_2 $BB1_2 $BB1_2 $BB1_3 $BB1_3 $BB1_3 $BB1_3 $BB1_3 $BB1_3 $BB1_3 $BB1_3 $BB1_4 $BB1_4 $BB1_4 $BB1_4 $BB1_4 $BB1_4 $BB1_5 $BB1_6 $BB1_7)
|
||||
; CHECk: BB1_2:
|
||||
; CHECK: (setlocal {{.*}} (global $foo0))
|
||||
; CHECK: BB1_3:
|
||||
; CHECK: (setlocal {{.*}} (global $foo1))
|
||||
; CHECK: BB1_4:
|
||||
; CHECK: (setlocal {{.*}} (global $foo2))
|
||||
; CHECK: BB1_5:
|
||||
; CHECK: (setlocal {{.*}} (global $foo3))
|
||||
; CHECK: BB1_6:
|
||||
; CHECK: (setlocal {{.*}} (global $foo4))
|
||||
; CHECK: BB1_7:
|
||||
; CHECK: (setlocal {{.*}} (global $foo5))
|
||||
; CHECK: BB1_8:
|
||||
; CHECK: (return)
|
||||
define void @bar64(i64 %n) {
|
||||
entry:
|
||||
switch i64 %n, label %sw.epilog [
|
||||
i64 0, label %sw.bb
|
||||
i64 1, label %sw.bb
|
||||
i64 2, label %sw.bb
|
||||
i64 3, label %sw.bb
|
||||
i64 4, label %sw.bb
|
||||
i64 5, label %sw.bb
|
||||
i64 6, label %sw.bb
|
||||
i64 7, label %sw.bb.1
|
||||
i64 8, label %sw.bb.1
|
||||
i64 9, label %sw.bb.1
|
||||
i64 10, label %sw.bb.1
|
||||
i64 11, label %sw.bb.1
|
||||
i64 12, label %sw.bb.1
|
||||
i64 13, label %sw.bb.1
|
||||
i64 14, label %sw.bb.1
|
||||
i64 15, label %sw.bb.2
|
||||
i64 16, label %sw.bb.2
|
||||
i64 17, label %sw.bb.2
|
||||
i64 18, label %sw.bb.2
|
||||
i64 19, label %sw.bb.2
|
||||
i64 20, label %sw.bb.2
|
||||
i64 21, label %sw.bb.3
|
||||
i64 22, label %sw.bb.4
|
||||
i64 23, label %sw.bb.5
|
||||
]
|
||||
|
||||
sw.bb: ; preds = %entry, %entry, %entry, %entry, %entry, %entry, %entry
|
||||
tail call void @foo0()
|
||||
br label %sw.epilog
|
||||
|
||||
sw.bb.1: ; preds = %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry
|
||||
tail call void @foo1()
|
||||
br label %sw.epilog
|
||||
|
||||
sw.bb.2: ; preds = %entry, %entry, %entry, %entry, %entry, %entry
|
||||
tail call void @foo2()
|
||||
br label %sw.epilog
|
||||
|
||||
sw.bb.3: ; preds = %entry
|
||||
tail call void @foo3()
|
||||
br label %sw.epilog
|
||||
|
||||
sw.bb.4: ; preds = %entry
|
||||
tail call void @foo4()
|
||||
br label %sw.epilog
|
||||
|
||||
sw.bb.5: ; preds = %entry
|
||||
tail call void @foo5()
|
||||
br label %sw.epilog
|
||||
|
||||
sw.epilog: ; preds = %entry, %sw.bb.5, %sw.bb.4, %sw.bb.3, %sw.bb.2, %sw.bb.1, %sw.bb
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user