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[Thumb] Don't try and emit LDRH/LDRB from the constant pool
This is not a valid encoding - these instructions cannot do PC-relative addressing. The underlying problem here is of whitelist in ARMISelDAGToDAG that unwraps ARMISD::Wrappers during addressing-mode selection. This didn't realise TargetConstantPool was actually possible, so didn't handle it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283323 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1188,6 +1188,7 @@ ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
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} else if (N.getOpcode() == ARMISD::Wrapper &&
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N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress &&
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N.getOperand(0).getOpcode() != ISD::TargetExternalSymbol &&
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N.getOperand(0).getOpcode() != ISD::TargetConstantPool &&
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N.getOperand(0).getOpcode() != ISD::TargetGlobalTLSAddress) {
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Base = N.getOperand(0);
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} else {
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22
test/CodeGen/ARM/constantpool-promote-ldrh.ll
Normal file
22
test/CodeGen/ARM/constantpool-promote-ldrh.ll
Normal file
@ -0,0 +1,22 @@
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; RUN: llc < %s -O0 -fast-isel=false | FileCheck %s
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; RUN: llc < %s -O0 -fast-isel=false -filetype=obj
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv6m-arm-linux-gnueabi"
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@fn1.a = private unnamed_addr constant [4 x i16] [i16 6, i16 0, i16 0, i16 0], align 2
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; We must not try and emit this bad instruction: "ldrh r1, .LCPI0_0"
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; CHECK-LABEL: fn1:
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; CHECK: adr [[base:r[0-9]+]], .LCPI0_0
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; CHECK-NOT: ldrh {{r[0-9]+}}, .LCPI0_0
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; FIXME: We want to use [[base]] below instead of "r0", but the preceding square bracket confuses FileCheck.
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; CHECK: ldrh r{{[0-9]+}}, [r0]
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define hidden i32 @fn1() #0 {
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entry:
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call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* bitcast ([4 x i16]* @fn1.a to i8*), i32 8, i32 2, i1 false)
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ret i32 undef
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}
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; Function Attrs: argmemonly nounwind
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declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i32, i1)
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attributes #0 = { "target-features"="+strict-align" }
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