[Thumb] Don't try and emit LDRH/LDRB from the constant pool

This is not a valid encoding - these instructions cannot do PC-relative addressing.

The underlying problem here is of whitelist in ARMISelDAGToDAG that unwraps ARMISD::Wrappers during addressing-mode selection. This didn't realise TargetConstantPool was actually possible, so didn't handle it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283323 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
James Molloy 2016-10-05 14:52:13 +00:00
parent 471e2909de
commit 71beb002a1
2 changed files with 23 additions and 0 deletions

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@ -1188,6 +1188,7 @@ ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
} else if (N.getOpcode() == ARMISD::Wrapper &&
N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress &&
N.getOperand(0).getOpcode() != ISD::TargetExternalSymbol &&
N.getOperand(0).getOpcode() != ISD::TargetConstantPool &&
N.getOperand(0).getOpcode() != ISD::TargetGlobalTLSAddress) {
Base = N.getOperand(0);
} else {

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@ -0,0 +1,22 @@
; RUN: llc < %s -O0 -fast-isel=false | FileCheck %s
; RUN: llc < %s -O0 -fast-isel=false -filetype=obj
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv6m-arm-linux-gnueabi"
@fn1.a = private unnamed_addr constant [4 x i16] [i16 6, i16 0, i16 0, i16 0], align 2
; We must not try and emit this bad instruction: "ldrh r1, .LCPI0_0"
; CHECK-LABEL: fn1:
; CHECK: adr [[base:r[0-9]+]], .LCPI0_0
; CHECK-NOT: ldrh {{r[0-9]+}}, .LCPI0_0
; FIXME: We want to use [[base]] below instead of "r0", but the preceding square bracket confuses FileCheck.
; CHECK: ldrh r{{[0-9]+}}, [r0]
define hidden i32 @fn1() #0 {
entry:
call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* bitcast ([4 x i16]* @fn1.a to i8*), i32 8, i32 2, i1 false)
ret i32 undef
}
; Function Attrs: argmemonly nounwind
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i32, i1)
attributes #0 = { "target-features"="+strict-align" }