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ARM: introduce llvm.arm.undefined intrinsic

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This intrinsic permits the emission of platform specific undefined sequences.
ARM has reserved the 0xde opcode which takes a single integer parameter (ignored
by the CPU).  This permits the operating system to implement custom behaviour on
this trap.  The llvm.arm.undefined intrinsic is meant to provide a means for
generating the target specific behaviour from the frontend.  This is
particularly useful for Windows on ARM which has made use of a series of these
special opcodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209390 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Saleem Abdulrasool 2014-05-22 04:46:46 +00:00
parent bce7d05ba9
commit 71ce2118bb
5 changed files with 24 additions and 5 deletions
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5
include/llvm/IR/IntrinsicsARM.td
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@ -125,6 +125,11 @@ def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
def int_arm_hint : Intrinsic<[], [llvm_i32_ty]>;
//===----------------------------------------------------------------------===//
// UND (reserved undefined sequence)
def int_arm_undefined : Intrinsic<[], [llvm_i32_ty]>;
//===----------------------------------------------------------------------===//
// Advanced SIMD (NEON)

2
lib/Target/ARM/ARMInstrInfo.td
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@ -1969,7 +1969,7 @@ def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
// A8.8.247 UDF - Undefined (Encoding A1)
def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary,
"udf", "\t$imm16", []> {
"udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> {
bits<16> imm16;
let Inst{31-28} = 0b1110; // AL
let Inst{27-25} = 0b011;

4
lib/Target/ARM/ARMInstrThumb.td
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@ -1194,8 +1194,8 @@ def tTST : // A8.6.230
Sched<[WriteALU]>;
// A8.8.247 UDF - Undefined (Encoding T1)
def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8", []>,
Encoding16 {
def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8",
[(int_arm_undefined imm0_255:$imm8)]>, Encoding16 {
bits<8> imm8;
let Inst{15-12} = 0b1101;
let Inst{11-8} = 0b1110;

4
lib/Target/ARM/ARMInstrThumb2.td
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@ -2408,8 +2408,8 @@ def t2UBFX: T2TwoRegBitFI<
}
// A8.8.247 UDF - Undefined (Encoding T2)
def t2UDF
: T2XI<(outs), (ins imm0_65535:$imm16), IIC_Br, "udf.w\t$imm16", []> {
def t2UDF : T2XI<(outs), (ins imm0_65535:$imm16), IIC_Br, "udf.w\t$imm16",
[(int_arm_undefined imm0_65535:$imm16)]> {
bits<16> imm16;
let Inst{31-29} = 0b111;
let Inst{28-27} = 0b10;

14
test/CodeGen/ARM/undefined.ll Normal file
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@ -0,0 +1,14 @@
; RUN: llc -mtriple armv7-eabi -o - %s | FileCheck %s
; RUN: llc -mtriple thumbv6m-eabi -o - %s | FileCheck %s
; RUN: llc -mtriple thumbv7-eabi -o - %s | FileCheck %s
declare void @llvm.arm.undefined(i32) nounwind
define void @undefined_trap() {
entry:
tail call void @llvm.arm.undefined(i32 254)
ret void
}
; CHECK-LABEL: undefined_trap
; CHECK: udf #254