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Uncomment assertions that register# != 0 on calls to

Browse Source 
MRegisterInfo::is{Physical,Virtual}Register. Apply appropriate fixes
to relevant files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11882 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alkis Evlogimenos 2004-02-26 22:00:20 +00:00
parent 0550256c31
commit 71e353ed35
6 changed files with 35 additions and 27 deletions
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4
include/llvm/Target/MRegisterInfo.h
View File

@ -141,14 +141,14 @@ public:
/// isPhysicalRegister - Return true if the specified register number is in
/// the physical register namespace.
static bool isPhysicalRegister(unsigned Reg) {
// assert(Reg && "this is not a register!");
assert(Reg && "this is not a register!");
return Reg < FirstVirtualRegister;
}
/// isVirtualRegister - Return true if the specified register number is in
/// the virtual register namespace.
static bool isVirtualRegister(unsigned Reg) {
// assert(Reg && "this is not a register!");
assert(Reg && "this is not a register!");
return Reg >= FirstVirtualRegister;
}

4
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -134,7 +134,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
mii != mie; ) {
for (unsigned i = 0; i < mii->getNumOperands(); ++i) {
const MachineOperand& mop = mii->getOperand(i);
if (mop.isRegister()) {
if (mop.isRegister() && mop.getReg()) {
// replace register with representative register
unsigned reg = rep(mop.getReg());
mii->SetMachineOperandReg(i, reg);
@ -421,7 +421,7 @@ void LiveIntervals::computeIntervals()
for (int i = mi->getNumOperands() - 1; i >= 0; --i) {
MachineOperand& mop = mi->getOperand(i);
// handle register defs - build intervals
if (mop.isRegister() && mop.isDef())
if (mop.isRegister() && mop.getReg() && mop.isDef())
handleRegisterDef(mbb, mi, mop.getReg());
}
}

6
lib/CodeGen/LiveVariables.cpp
View File

@ -232,7 +232,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
// Process all explicit uses...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isUse() && MO.isRegister()) {
if (MO.isUse() && MO.isRegister() && MO.getReg()) {
if (MRegisterInfo::isVirtualRegister(MO.getReg())){
HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
} else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
@ -250,7 +250,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
// Process all explicit defs...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isDef() && MO.isRegister()) {
if (MO.isDef() && MO.isRegister() && MO.getReg()) {
if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
VarInfo &VRInfo = getVarInfo(MO.getReg());
@ -325,7 +325,7 @@ void LiveVariables::instructionChanged(MachineInstr *OldMI,
// the instruction.
for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = NewMI->getOperand(i);
if (MO.isRegister() && MO.isDef() &&
if (MO.isRegister() && MO.isDef() && MO.getReg() &&
MRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned Reg = MO.getReg();
VarInfo &VI = getVarInfo(Reg);

30
lib/CodeGen/RegAllocLocal.cpp
View File

@ -542,11 +542,13 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
// physical register is referenced by the instruction, that it is guaranteed
// to be live-in, or the input is badly hosed.
//
for (unsigned i = 0; i != MI->getNumOperands(); ++i)
if (MI->getOperand(i).isUse() &&
!MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
MRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
MachineOperand& MO = MI->getOperand(i);
// here we are looking for only used operands (never def&use)
if (!MO.isDef() && MO.isRegister() && MO.getReg() &&
MRegisterInfo::isVirtualRegister(MO.getReg()))
MI = reloadVirtReg(MBB, MI, i);
}
// If this instruction is the last user of anything in registers, kill the
// value, freeing the register being used, so it doesn't need to be
@ -573,10 +575,11 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
// Loop over all of the operands of the instruction, spilling registers that
// are defined, and marking explicit destinations in the PhysRegsUsed map.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
if (MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
MRegisterInfo::isPhysicalRegister(MI->getOperand(i).getReg())) {
unsigned Reg = MI->getOperand(i).getReg();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
if (MO.isDef() && MO.isRegister() && MO.getReg() &&
MRegisterInfo::isPhysicalRegister(MO.getReg())) {
unsigned Reg = MO.getReg();
spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in the reg
PhysRegsUsed[Reg] = 0; // It is free and reserved now
PhysRegsUseOrder.push_back(Reg);
@ -586,6 +589,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
}
}
}
// Loop over the implicit defs, spilling them as well.
for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
@ -606,10 +610,11 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
// implicit defs and assign them to a register, spilling incoming values if
// we need to scavenge a register.
//
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
if (MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
MRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg())) {
unsigned DestVirtReg = MI->getOperand(i).getReg();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
if (MO.isDef() && MO.isRegister() && MO.getReg() &&
MRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned DestVirtReg = MO.getReg();
unsigned DestPhysReg;
// If DestVirtReg already has a value, use it.
@ -618,6 +623,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
markVirtRegModified(DestVirtReg);
MI->SetMachineOperandReg(i, DestPhysReg); // Assign the output register
}
}
// If this instruction defines any registers that are immediately dead,
// kill them now.

9
lib/Target/X86/InstSelectSimple.cpp
View File

@ -696,14 +696,15 @@ void ISel::InsertFPRegKills() {
for (MachineFunction::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I!=E; ++I)
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
if (I->getOperand(i).isRegister()) {
unsigned Reg = I->getOperand(i).getReg();
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
MachineOperand& MO = I->getOperand(i);
if (MO.isRegister() && MO.getReg()) {
unsigned Reg = MO.getReg();
if (MRegisterInfo::isVirtualRegister(Reg))
if (RegMap.getRegClass(Reg)->getSize() == 10)
goto UsesFPReg;
}
}
// If we haven't found an FP register use or def in this basic block, check
// to see if any of our successors has an FP PHI node, which will cause a
// copy to be inserted into this block.

9
lib/Target/X86/X86ISelSimple.cpp
View File

@ -696,14 +696,15 @@ void ISel::InsertFPRegKills() {
for (MachineFunction::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I!=E; ++I)
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
if (I->getOperand(i).isRegister()) {
unsigned Reg = I->getOperand(i).getReg();
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
MachineOperand& MO = I->getOperand(i);
if (MO.isRegister() && MO.getReg()) {
unsigned Reg = MO.getReg();
if (MRegisterInfo::isVirtualRegister(Reg))
if (RegMap.getRegClass(Reg)->getSize() == 10)
goto UsesFPReg;
}
}
// If we haven't found an FP register use or def in this basic block, check
// to see if any of our successors has an FP PHI node, which will cause a
// copy to be inserted into this block.