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Don't repeat function/variable name in comment. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218791 91177308-0d34-0410-b5e6-96231b3b80d8
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lib/Target/X86
@ -13821,8 +13821,7 @@ static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
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return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
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}
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// LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
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//
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// Check whether an OR'd tree is PTEST-able.
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static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
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@ -354,9 +354,9 @@ namespace llvm {
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VINSERT,
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VEXTRACT,
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// PMULUDQ - Vector multiply packed unsigned doubleword integers
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// Vector multiply packed unsigned doubleword integers
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PMULUDQ,
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// PMULUDQ - Vector multiply packed signed doubleword integers
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// Vector multiply packed signed doubleword integers
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PMULDQ,
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// FMA nodes
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@ -367,20 +367,19 @@ namespace llvm {
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FMADDSUB,
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FMSUBADD,
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// VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
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// according to %al. An operator is needed so that this can be expanded
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// with control flow.
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// Save xmm argument registers to the stack, according to %al. An operator
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// is needed so that this can be expanded with control flow.
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VASTART_SAVE_XMM_REGS,
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// WIN_ALLOCA - Windows's _chkstk call to do stack probing.
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// Windows's _chkstk call to do stack probing.
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WIN_ALLOCA,
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// SEG_ALLOCA - For allocating variable amounts of stack space when using
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// For allocating variable amounts of stack space when using
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// segmented stacks. Check if the current stacklet has enough space, and
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// falls back to heap allocation if not.
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SEG_ALLOCA,
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// WIN_FTOL - Windows's _ftol2 runtime routine to do fptoui.
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// Windows's _ftol2 runtime routine to do fptoui.
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WIN_FTOL,
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// Memory barrier
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@ -389,38 +388,37 @@ namespace llvm {
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SFENCE,
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LFENCE,
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// FNSTSW16r - Store FP status word into i16 register.
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// Store FP status word into i16 register.
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FNSTSW16r,
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// SAHF - Store contents of %ah into %eflags.
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// Store contents of %ah into %eflags.
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SAHF,
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// RDRAND - Get a random integer and indicate whether it is valid in CF.
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// Get a random integer and indicate whether it is valid in CF.
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RDRAND,
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// RDSEED - Get a NIST SP800-90B & C compliant random integer and
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// Get a NIST SP800-90B & C compliant random integer and
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// indicate whether it is valid in CF.
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RDSEED,
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// PCMP*STRI
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PCMPISTRI,
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PCMPESTRI,
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// XTEST - Test if in transactional execution.
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// Test if in transactional execution.
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XTEST,
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// LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap.
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// Compare and swap.
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LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
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LCMPXCHG8_DAG,
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LCMPXCHG16_DAG,
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// VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
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// Load, scalar_to_vector, and zero extend.
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VZEXT_LOAD,
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// FNSTCW16m - Store FP control world into i16 memory.
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// Store FP control world into i16 memory.
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FNSTCW16m,
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/// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
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/// This instruction implements FP_TO_SINT with the
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/// integer destination in memory and a FP reg source. This corresponds
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/// to the X86::FIST*m instructions and the rounding mode change stuff. It
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/// has two inputs (token chain and address) and two outputs (int value
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@ -429,7 +427,7 @@ namespace llvm {
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FP_TO_INT32_IN_MEM,
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FP_TO_INT64_IN_MEM,
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/// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
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/// This instruction implements SINT_TO_FP with the
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/// integer source in memory and FP reg result. This corresponds to the
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/// X86::FILD*m instructions. It has three inputs (token chain, address,
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/// and source type) and two outputs (FP value and token chain). FILD_FLAG
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@ -437,19 +435,19 @@ namespace llvm {
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FILD,
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FILD_FLAG,
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/// FLD - This instruction implements an extending load to FP stack slots.
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/// This instruction implements an extending load to FP stack slots.
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/// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
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/// operand, ptr to load from, and a ValueType node indicating the type
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/// to load to.
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FLD,
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/// FST - This instruction implements a truncating store to FP stack
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/// This instruction implements a truncating store to FP stack
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/// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
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/// chain operand, value to store, address, and a ValueType to store it
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/// as.
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FST,
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/// VAARG_64 - This instruction grabs the address of the next argument
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/// This instruction grabs the address of the next argument
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/// from a va_list. (reads and modifies the va_list in memory)
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VAARG_64
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@ -461,57 +459,56 @@ namespace llvm {
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/// Define some predicates that are used for node matching.
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namespace X86 {
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/// isVEXTRACT128Index - Return true if the specified
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/// Return true if the specified
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/// EXTRACT_SUBVECTOR operand specifies a vector extract that is
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/// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
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bool isVEXTRACT128Index(SDNode *N);
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/// isVINSERT128Index - Return true if the specified
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/// Return true if the specified
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/// INSERT_SUBVECTOR operand specifies a subvector insert that is
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/// suitable for input to VINSERTF128, VINSERTI128 instructions.
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bool isVINSERT128Index(SDNode *N);
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/// isVEXTRACT256Index - Return true if the specified
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/// Return true if the specified
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/// EXTRACT_SUBVECTOR operand specifies a vector extract that is
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/// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
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bool isVEXTRACT256Index(SDNode *N);
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/// isVINSERT256Index - Return true if the specified
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/// Return true if the specified
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/// INSERT_SUBVECTOR operand specifies a subvector insert that is
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/// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
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bool isVINSERT256Index(SDNode *N);
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/// getExtractVEXTRACT128Immediate - Return the appropriate
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/// Return the appropriate
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/// immediate to extract the specified EXTRACT_SUBVECTOR index
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/// with VEXTRACTF128, VEXTRACTI128 instructions.
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unsigned getExtractVEXTRACT128Immediate(SDNode *N);
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/// getInsertVINSERT128Immediate - Return the appropriate
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/// Return the appropriate
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/// immediate to insert at the specified INSERT_SUBVECTOR index
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/// with VINSERTF128, VINSERT128 instructions.
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unsigned getInsertVINSERT128Immediate(SDNode *N);
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/// getExtractVEXTRACT256Immediate - Return the appropriate
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/// Return the appropriate
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/// immediate to extract the specified EXTRACT_SUBVECTOR index
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/// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
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unsigned getExtractVEXTRACT256Immediate(SDNode *N);
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/// getInsertVINSERT256Immediate - Return the appropriate
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/// Return the appropriate
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/// immediate to insert at the specified INSERT_SUBVECTOR index
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/// with VINSERTF64x4, VINSERTI64x4 instructions.
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unsigned getInsertVINSERT256Immediate(SDNode *N);
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/// isZeroNode - Returns true if Elt is a constant zero or a floating point
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/// constant +0.0.
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/// Returns true if Elt is a constant zero or floating point constant +0.0.
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bool isZeroNode(SDValue Elt);
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/// isOffsetSuitableForCodeModel - Returns true of the given offset can be
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/// Returns true of the given offset can be
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/// fit into displacement field of the instruction.
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bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
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bool hasSymbolicDisplacement = true);
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/// isCalleePop - Determines whether the callee is required to pop its
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/// Determines whether the callee is required to pop its
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/// own arguments. Callee pop is necessary to support tail calls.
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bool isCalleePop(CallingConv::ID CallingConv,
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bool is64Bit, bool IsVarArg, bool TailCallOpt);
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@ -528,7 +525,7 @@ namespace llvm {
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}
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//===--------------------------------------------------------------------===//
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// X86TargetLowering - X86 Implementation of the TargetLowering interface
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// X86 Implementation of the TargetLowering interface
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class X86TargetLowering final : public TargetLowering {
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public:
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explicit X86TargetLowering(X86TargetMachine &TM);
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@ -542,21 +539,20 @@ namespace llvm {
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const MachineBasicBlock *MBB, unsigned uid,
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MCContext &Ctx) const override;
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/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
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/// jumptable.
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/// Returns relocation base for the given PIC jumptable.
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SDValue getPICJumpTableRelocBase(SDValue Table,
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SelectionDAG &DAG) const override;
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const MCExpr *
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getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
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unsigned JTI, MCContext &Ctx) const override;
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/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
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/// Return the desired alignment for ByVal aggregate
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/// function arguments in the caller parameter area. For X86, aggregates
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/// that contains are placed at 16-byte boundaries while the rest are at
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/// 4-byte boundaries.
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unsigned getByValTypeAlignment(Type *Ty) const override;
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/// getOptimalMemOpType - Returns the target specific optimal type for load
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/// Returns the target specific optimal type for load
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/// and store operations as a result of memset, memcpy, and memmove
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/// lowering. If DstAlign is zero that means it's safe to destination
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/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
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@ -571,7 +567,7 @@ namespace llvm {
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bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
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MachineFunction &MF) const override;
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/// isSafeMemOpType - Returns true if it's safe to use load / store of the
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/// Returns true if it's safe to use load / store of the
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/// specified type to expand memcpy / memset inline. This is mostly true
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/// for all types except for some special cases. For example, on X86
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/// targets without SSE2 f64 load / store are done with fldl / fstpl which
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@ -579,17 +575,17 @@ namespace llvm {
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/// legal as the hook is used before type legalization.
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bool isSafeMemOpType(MVT VT) const override;
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/// allowsMisalignedMemoryAccesses - Returns true if the target allows
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/// Returns true if the target allows
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/// unaligned memory accesses. of the specified type. Returns whether it
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/// is "fast" by reference in the second argument.
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bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
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bool *Fast) const override;
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/// LowerOperation - Provide custom lowering hooks for some operations.
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/// Provide custom lowering hooks for some operations.
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///
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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/// ReplaceNodeResults - Replace the results of node with an illegal result
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/// Replace the results of node with an illegal result
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/// type with new values built out of custom code.
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///
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void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
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@ -598,13 +594,13 @@ namespace llvm {
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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/// isTypeDesirableForOp - Return true if the target has native support for
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/// Return true if the target has native support for
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/// the specified value type and it is 'desirable' to use the type for the
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/// given node type. e.g. On x86 i16 is legal, but undesirable since i16
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/// instruction encodings are longer and some i16 instructions are slow.
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bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
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/// isTypeDesirable - Return true if the target has native support for the
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/// Return true if the target has native support for the
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/// specified value type and it is 'desirable' to use the type. e.g. On x86
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/// i16 is legal, but undesirable since i16 instruction encodings are longer
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/// and some i16 instructions are slow.
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@ -615,24 +611,21 @@ namespace llvm {
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MachineBasicBlock *MBB) const override;
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/// getTargetNodeName - This method returns the name of a target specific
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/// DAG node.
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/// This method returns the name of a target specific DAG node.
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const char *getTargetNodeName(unsigned Opcode) const override;
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/// getSetCCResultType - Return the value type to use for ISD::SETCC.
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/// Return the value type to use for ISD::SETCC.
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EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
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/// computeKnownBitsForTargetNode - Determine which of the bits specified
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/// in Mask are known to be either zero or one and return them in the
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/// KnownZero/KnownOne bitsets.
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/// Determine which of the bits specified in Mask are known to be either
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/// zero or one and return them in the KnownZero/KnownOne bitsets.
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void computeKnownBitsForTargetNode(const SDValue Op,
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APInt &KnownZero,
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APInt &KnownOne,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const override;
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// ComputeNumSignBitsForTargetNode - Determine the number of bits in the
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// operation that are sign bits.
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/// Determine the number of bits in the operation that are sign bits.
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unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
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const SelectionDAG &DAG,
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unsigned Depth) const override;
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@ -655,16 +648,15 @@ namespace llvm {
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const char *LowerXConstraint(EVT ConstraintVT) const override;
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/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
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/// true it means one of the asm constraint of the inline asm instruction
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/// being processed is 'm'.
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/// Lower the specified operand into the Ops vector. If it is invalid, don't
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/// add anything to Ops. If hasMemory is true it means one of the asm
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/// constraint of the inline asm instruction being processed is 'm'.
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void LowerAsmOperandForConstraint(SDValue Op,
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std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const override;
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/// getRegForInlineAsmConstraint - Given a physical register constraint
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/// Given a physical register constraint
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/// (e.g. {edx}), return the register number and the register class for the
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/// register. This should only be used for C_Register constraints. On
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/// error, this returns a register number of 0.
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@ -672,17 +664,17 @@ namespace llvm {
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getRegForInlineAsmConstraint(const std::string &Constraint,
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MVT VT) const override;
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type.
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bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
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/// isLegalICmpImmediate - Return true if the specified immediate is legal
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/// Return true if the specified immediate is legal
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/// icmp immediate, that is the target has icmp instructions which can
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/// compare a register against the immediate without having to materialize
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/// the immediate into a register.
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bool isLegalICmpImmediate(int64_t Imm) const override;
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/// isLegalAddImmediate - Return true if the specified immediate is legal
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/// Return true if the specified immediate is legal
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/// add immediate, that is the target has add instructions which can
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/// add a register and the immediate without having to materialize
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/// the immediate into a register.
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@ -697,7 +689,7 @@ namespace llvm {
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bool isVectorShiftByScalarCheap(Type *Ty) const override;
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/// isTruncateFree - Return true if it's free to truncate a value of
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/// Return true if it's free to truncate a value of
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/// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
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/// register EAX to i16 by referencing its sub-register AX.
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bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
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@ -705,7 +697,7 @@ namespace llvm {
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bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
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/// isZExtFree - Return true if any actual instruction that defines a
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/// Return true if any actual instruction that defines a
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/// value of type Ty1 implicit zero-extends the value to Ty2 in the result
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/// register. This does not necessarily include registers defined in
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/// unknown ways, such as incoming arguments, or copies from unknown
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@ -717,37 +709,35 @@ namespace llvm {
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bool isZExtFree(EVT VT1, EVT VT2) const override;
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bool isZExtFree(SDValue Val, EVT VT2) const override;
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/// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
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/// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
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/// expanded to FMAs when this method returns true, otherwise fmuladd is
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/// expanded to fmul + fadd.
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/// Return true if an FMA operation is faster than a pair of fmul and fadd
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/// instructions. fmuladd intrinsics will be expanded to FMAs when this
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/// method returns true, otherwise fmuladd is expanded to fmul + fadd.
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bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
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/// isNarrowingProfitable - Return true if it's profitable to narrow
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/// Return true if it's profitable to narrow
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/// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
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/// from i32 to i8 but not from i32 to i16.
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bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
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/// isFPImmLegal - Returns true if the target can instruction select the
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/// Returns true if the target can instruction select the
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/// specified FP immediate natively. If false, the legalizer will
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/// materialize the FP immediate as a load from a constant pool.
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bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
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/// isShuffleMaskLegal - Targets can use this to indicate that they only
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/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
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/// By default, if a target supports the VECTOR_SHUFFLE node, all mask
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/// values are assumed to be legal.
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/// Targets can use this to indicate that they only support *some*
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/// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
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/// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
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/// be legal.
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bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
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EVT VT) const override;
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/// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
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/// used by Targets can use this to indicate if there is a suitable
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/// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
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/// pool entry.
|
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/// Similar to isShuffleMaskLegal. This is used by Targets can use this to
|
||||
/// indicate if there is a suitable VECTOR_SHUFFLE that can be used to
|
||||
/// replace a VAND with a constant pool entry.
|
||||
bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
|
||||
EVT VT) const override;
|
||||
|
||||
/// ShouldShrinkFPConstant - If true, then instruction selection should
|
||||
/// If true, then instruction selection should
|
||||
/// seek to shrink the FP constant of the specified type to a smaller type
|
||||
/// in order to save space and / or reduce runtime.
|
||||
bool ShouldShrinkFPConstant(EVT VT) const override {
|
||||
@ -761,19 +751,18 @@ namespace llvm {
|
||||
return Subtarget;
|
||||
}
|
||||
|
||||
/// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
|
||||
/// computed in an SSE register, not on the X87 floating point stack.
|
||||
/// Return true if the specified scalar FP type is computed in an SSE
|
||||
/// register, not on the X87 floating point stack.
|
||||
bool isScalarFPTypeInSSEReg(EVT VT) const {
|
||||
return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
|
||||
(VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
|
||||
}
|
||||
|
||||
/// isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine
|
||||
/// for fptoui.
|
||||
/// Return true if the target uses the MSVC _ftol2 routine for fptoui.
|
||||
bool isTargetFTOL() const;
|
||||
|
||||
/// isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be
|
||||
/// used for fptoui to the given type.
|
||||
/// Return true if the MSVC _ftol2 routine should be used for fptoui to the
|
||||
/// given type.
|
||||
bool isIntegerTypeFTOL(EVT VT) const {
|
||||
return isTargetFTOL() && VT == MVT::i64;
|
||||
}
|
||||
@ -790,15 +779,14 @@ namespace llvm {
|
||||
|
||||
unsigned getRegisterByName(const char* RegName, EVT VT) const override;
|
||||
|
||||
/// createFastISel - This method returns a target specific FastISel object,
|
||||
/// This method returns a target specific FastISel object,
|
||||
/// or null if the target does not support "fast" ISel.
|
||||
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
|
||||
const TargetLibraryInfo *libInfo) const override;
|
||||
|
||||
/// getStackCookieLocation - Return true if the target stores stack
|
||||
/// protector cookies at a fixed offset in some non-standard address
|
||||
/// space, and populates the address space and offset as
|
||||
/// appropriate.
|
||||
/// Return true if the target stores stack protector cookies at a fixed
|
||||
/// offset in some non-standard address space, and populates the address
|
||||
/// space and offset as appropriate.
|
||||
bool getStackCookieLocation(unsigned &AddressSpace,
|
||||
unsigned &Offset) const override;
|
||||
|
||||
@ -819,7 +807,7 @@ namespace llvm {
|
||||
findRepresentativeClass(MVT VT) const override;
|
||||
|
||||
private:
|
||||
/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
|
||||
/// Keep a pointer to the X86Subtarget around so that we can
|
||||
/// make the right decision when generating code for different targets.
|
||||
const X86Subtarget *Subtarget;
|
||||
const DataLayout *TD;
|
||||
@ -828,17 +816,16 @@ namespace llvm {
|
||||
/// the operation actions unless we have to.
|
||||
TargetOptions TO;
|
||||
|
||||
/// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
|
||||
/// floating point ops.
|
||||
/// Select between SSE or x87 floating point ops.
|
||||
/// When SSE is available, use it for f32 operations.
|
||||
/// When SSE2 is available, use it for f64 operations.
|
||||
bool X86ScalarSSEf32;
|
||||
bool X86ScalarSSEf64;
|
||||
|
||||
/// LegalFPImmediates - A list of legal fp immediates.
|
||||
/// A list of legal FP immediates.
|
||||
std::vector<APFloat> LegalFPImmediates;
|
||||
|
||||
/// addLegalFPImmediate - Indicate that this x86 target can instruction
|
||||
/// Indicate that this x86 target can instruction
|
||||
/// select the specified FP immediate natively.
|
||||
void addLegalFPImmediate(const APFloat& Imm) {
|
||||
LegalFPImmediates.push_back(Imm);
|
||||
@ -862,9 +849,8 @@ namespace llvm {
|
||||
|
||||
// Call lowering helpers.
|
||||
|
||||
/// IsEligibleForTailCallOptimization - Check whether the call is eligible
|
||||
/// for tail call optimization. Targets which want to do tail call
|
||||
/// optimization should implement this function.
|
||||
/// Check whether the call is eligible for tail call optimization. Targets
|
||||
/// that want to do tail call optimization should implement this function.
|
||||
bool IsEligibleForTailCallOptimization(SDValue Callee,
|
||||
CallingConv::ID CalleeCC,
|
||||
bool isVarArg,
|
||||
|
Loading…
Reference in New Issue
Block a user