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Rolling back the AVX support patch due to breaking a gcc 4.6 build bot that doesn't understand the xgetbv instruction for some reason. Will revisit when time permits.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178614 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Aaron Ballman 2013-04-03 03:11:39 +00:00
parent a67a20c95f
commit 729c19482f
1 changed files with 2 additions and 23 deletions
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25
lib/Support/Host.cpp
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@ -112,19 +112,6 @@ static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX,
#endif #endif
} }
static bool OSHasAVXSupport() {
#if defined( __GNUC__ ) && \
(__GNUC__ > 4 || __GNUC__ == 4 && __GNUC_MINOR__ >= 4)
int rEAX, rEDX;
__asm__ ("xgetbv" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
#elif defined(_MSC_VER)
unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
#else
int rEAX = 0; // Ensures we return false
#endif
return (rEAX & 6) == 6;
}
static void DetectX86FamilyModel(unsigned EAX, unsigned &Family, static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
unsigned &Model) { unsigned &Model) {
Family = (EAX >> 8) & 0xf; // Bits 8 - 11 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
@ -147,10 +134,6 @@ std::string sys::getHostCPUName() {
DetectX86FamilyModel(EAX, Family, Model); DetectX86FamilyModel(EAX, Family, Model);
bool HasSSE3 = (ECX & 0x1); bool HasSSE3 = (ECX & 0x1);
// If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
// indicates that the AVX registers will be saved and restored on context
// switch, when we have full AVX support.
bool HasAVX = (ECX & ((1 << 28) | (1 << 27))) != 0 && OSHasAVXSupport();
GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
bool Em64T = (EDX >> 29) & 0x1; bool Em64T = (EDX >> 29) & 0x1;
@ -260,15 +243,11 @@ std::string sys::getHostCPUName() {
case 42: // Intel Core i7 processor. All processors are manufactured case 42: // Intel Core i7 processor. All processors are manufactured
// using the 32 nm process. // using the 32 nm process.
case 45: case 45:
// Not all Sandy Bridge processors support AVX (such as the Pentium return "corei7-avx";
// versions instead of the i7 versions).
return HasAVX ? "corei7-avx" : "corei7";
// Ivy Bridge: // Ivy Bridge:
case 58: case 58:
// Not all Ivy Bridge processors support AVX (such as the Pentium return "core-avx-i";
// versions instead of the i7 versions).
return HasAVX ? "core-avx-i" : "corei7";
case 28: // Most 45 nm Intel Atom processors case 28: // Most 45 nm Intel Atom processors
case 38: // 45 nm Atom Lincroft case 38: // 45 nm Atom Lincroft