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Rolling back the AVX support patch due to breaking a gcc 4.6 build bot that doesn't understand the xgetbv instruction for some reason. Will revisit when time permits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178614 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -112,19 +112,6 @@ static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX,
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#endif
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}
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static bool OSHasAVXSupport() {
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#if defined( __GNUC__ ) && \
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(__GNUC__ > 4 || __GNUC__ == 4 && __GNUC_MINOR__ >= 4)
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int rEAX, rEDX;
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__asm__ ("xgetbv" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
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#elif defined(_MSC_VER)
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unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
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#else
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int rEAX = 0; // Ensures we return false
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#endif
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return (rEAX & 6) == 6;
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}
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static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
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unsigned &Model) {
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Family = (EAX >> 8) & 0xf; // Bits 8 - 11
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@ -147,10 +134,6 @@ std::string sys::getHostCPUName() {
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DetectX86FamilyModel(EAX, Family, Model);
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bool HasSSE3 = (ECX & 0x1);
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// If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
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// indicates that the AVX registers will be saved and restored on context
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// switch, when we have full AVX support.
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bool HasAVX = (ECX & ((1 << 28) | (1 << 27))) != 0 && OSHasAVXSupport();
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GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
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bool Em64T = (EDX >> 29) & 0x1;
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@ -260,15 +243,11 @@ std::string sys::getHostCPUName() {
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case 42: // Intel Core i7 processor. All processors are manufactured
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// using the 32 nm process.
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case 45:
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// Not all Sandy Bridge processors support AVX (such as the Pentium
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// versions instead of the i7 versions).
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return HasAVX ? "corei7-avx" : "corei7";
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return "corei7-avx";
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// Ivy Bridge:
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case 58:
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// Not all Ivy Bridge processors support AVX (such as the Pentium
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// versions instead of the i7 versions).
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return HasAVX ? "core-avx-i" : "corei7";
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return "core-avx-i";
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case 28: // Most 45 nm Intel Atom processors
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case 38: // 45 nm Atom Lincroft
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