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Handle v2i64 BUILD_VECTOR custom lowering correctly. v2i64 is a legal type,

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but i64 is not. If possible, change a i64 op to a f64 (e.g. load, constant)
and then cast it back.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27849 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-04-20 00:11:39 +00:00
parent 1014ab4470
commit 72cd9a9439
1 changed files with 16 additions and 1 deletions
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17
lib/Target/X86/X86ISelLowering.cpp
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@ -2980,7 +2980,22 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
if (Elt0IsZero) return Op;
// Zero extend a scalar to a vector.
return DAG.getNode(X86ISD::ZEXT_S2VEC, Op.getValueType(), Elt0);
if (Elt0.getValueType() != MVT::i64)
return DAG.getNode(X86ISD::ZEXT_S2VEC, Op.getValueType(), Elt0);
// See if we can turn it into a f64 op.
bool IsLegal = false;
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt0)) {
Elt0 = DAG.getConstantFP(BitsToDouble(C->getValue()), MVT::f64);
IsLegal = true;
} else if (Elt0.getOpcode() == ISD::LOAD) {
Elt0 = DAG.getLoad(MVT::f64, Elt0.getOperand(0), Elt0.getOperand(1),
Elt0.getOperand(2));
IsLegal = true;
}
if (IsLegal)
return DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64,
DAG.getNode(X86ISD::ZEXT_S2VEC, MVT::v2f64, Elt0));
}
if (Values.size() > 2) {