mirror of
https://github.com/RPCSX/llvm.git
synced 2025-01-27 07:12:06 +00:00
[Hexagon] Disable expanding MUX instructions that define a subregister
The code in HexagonExpandCondsets.cpp does not handle those cases at the moment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271281 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
4c77296fb2
commit
72f099b5f0
@ -991,6 +991,11 @@ bool HexagonExpandCondsets::predicate(MachineInstr *TfrI, bool Cond) {
|
||||
// some registers, which would complicate the transformation considerably.
|
||||
if (!MS.isKill())
|
||||
return false;
|
||||
// Avoid predicating instructions that define a subregister. The code
|
||||
// does not handle correctly cases where both subregisters of a register
|
||||
// are defined by a condset.
|
||||
if (MD.getSubReg())
|
||||
return false;
|
||||
|
||||
RegisterRef RT(MS);
|
||||
unsigned PredR = MP.getReg();
|
||||
|
Loading…
x
Reference in New Issue
Block a user