RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-12-15 07:59:50 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[Hexagon] Updating inline saturate lanes for v62 version.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297920 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2017-03-16 00:35:28 +00:00
parent e79427160e
commit 731cac0fcb
2 changed files with 17 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
View File

@ -105,7 +105,10 @@ void HexagonCVIResource::SetupTUL(TypeUnitsAndLanes *TUL, StringRef CPU) {
(*TUL)[HexagonII::TypeCVI_VP] = UnitsAndLanes(CVI_XLANE, 1);
(*TUL)[HexagonII::TypeCVI_VP_VS] = UnitsAndLanes(CVI_XLANE, 2);
(*TUL)[HexagonII::TypeCVI_VS] = UnitsAndLanes(CVI_SHIFT, 1);
(*TUL)[HexagonII::TypeCVI_VINLANESAT] = UnitsAndLanes(CVI_SHIFT, 1);
(*TUL)[HexagonII::TypeCVI_VINLANESAT] =
(CPU == "hexagonv60" || CPU == "hexagonv61" || CPU == "hexagonv61v1") ?
UnitsAndLanes(CVI_SHIFT, 1) :
UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
(*TUL)[HexagonII::TypeCVI_VM_LD] =
UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
(*TUL)[HexagonII::TypeCVI_VM_TMP_LD] = UnitsAndLanes(CVI_NONE, 0);

13
test/MC/Hexagon/bug20416.s Normal file
View File

@ -0,0 +1,13 @@
# RUN: not llvm-mc -mv60 -mhvx -filetype=asm %s 2>%t; FileCheck %s --check-prefix=CHECK-V60-ERROR <%t
# RUN: llvm-mc -mv62 -mhvx -filetype=asm %s | FileCheck %s
// for this a v60+/hvx instruction sequence, make sure fails with v60
// but passes with v62. this is because this instruction uses different
// itinerary between v60 and v62
{
v0.h=vsat(v5.w,v9.w)
v16.h=vsat(v6.w,v26.w)
}
# CHECK-V60-ERROR: rror: invalid instruction packet: slot error
# CHECK: v0.h = vsat(v5.w,v9.w)
# CHECK: v16.h = vsat(v6.w,v26.w)