RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-12-14 15:39:00 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

FNEG/FABS/UNDEF

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21029 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth 2005-04-02 19:11:07 +00:00
parent 30b46d41bc
commit 7332f3e05d
1 changed files with 13 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
lib/Target/Alpha/AlphaISelPattern.cpp
View File

@ -537,15 +537,19 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
Node->dump();
assert(0 && "Node not handled!\n");
case ISD::UNDEF: {
BuildMI(BB, Alpha::IDEF, 0, Result);
return Result;
}
case ISD::FNEG:
if(ISD::FABS == N.getOperand(0).getOpcode())
{
Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp1).addReg(Tmp1);
BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
} else {
Tmp1 = SelectExpr(N.getOperand(0));
Opc = DestType == MVT::f64 ? Alpha::SUBT : Alpha::SUBS ;
BuildMI(BB, Opc, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp1).addReg(Tmp1);
}
return Result;
@ -850,6 +854,12 @@ unsigned ISel::SelectExpr(SDOperand N) {
Node->dump();
assert(0 && "Node not handled!\n");
case ISD::UNDEF: {
BuildMI(BB, Alpha::IDEF, 0, Result);
return Result;
}
case ISD::DYNAMIC_STACKALLOC:
// Generate both result values.
if (Result != notIn)