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Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.

Browse Source 
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89711 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2009-11-23 23:20:51 +00:00
parent 0261d795f8
commit 735afe14ee
22 changed files with 2 additions and 108 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
include/llvm/CodeGen/SelectionDAGNodes.h
View File

@ -494,10 +494,9 @@ namespace ISD {
// Operand #last: Optional, an incoming flag.
INLINEASM,
// DBG_LABEL, EH_LABEL - Represents a label in mid basic block used to track
// EH_LABEL - Represents a label in mid basic block used to track
// locations needed for debug and exception handling tables. These nodes
// take a chain as input and return a chain.
DBG_LABEL,
EH_LABEL,
// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a
@ -546,12 +545,6 @@ namespace ISD {
// HANDLENODE node - Used as a handle for various purposes.
HANDLENODE,
// DEBUG_LOC - This node is used to represent source line information
// embedded in the code. It takes a token chain as input, then a line
// number, then a column then a file id (provided by MachineModuleInfo.) It
// produces a token chain as output.
DEBUG_LOC,
// TRAMPOLINE - This corresponds to the init_trampoline intrinsic.
// It takes as input a token chain, the pointer to the trampoline,
// the pointer to the nested function, the pointer to pass for the
@ -630,10 +623,6 @@ namespace ISD {
/// element is not an undef.
bool isScalarToVector(const SDNode *N);
/// isDebugLabel - Return true if the specified node represents a debug
/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node).
bool isDebugLabel(const SDNode *N);
//===--------------------------------------------------------------------===//
/// MemIndexedMode enum - This enum defines the load / store indexed
/// addressing modes.
@ -2031,8 +2020,7 @@ public:
static bool classof(const LabelSDNode *) { return true; }
static bool classof(const SDNode *N) {
return N->getOpcode() == ISD::DBG_LABEL ||
N->getOpcode() == ISD::EH_LABEL;
return N->getOpcode() == ISD::EH_LABEL;
}
};

7
include/llvm/Target/TargetSelectionDAG.td
View File

@ -864,10 +864,3 @@ class ComplexPattern<ValueType ty, int numops, string fn,
list<SDNodeProperty> Properties = props;
list<CPAttribute> Attributes = attrs;
}
//===----------------------------------------------------------------------===//
// Dwarf support.
//
def SDT_dwarf_loc : SDTypeProfile<0, 3,
[SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;

1
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -2243,7 +2243,6 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
break;
case ISD::EH_RETURN:
case ISD::DBG_LABEL:
case ISD::EH_LABEL:
case ISD::PREFETCH:
case ISD::MEMBARRIER:

18
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -200,19 +200,6 @@ bool ISD::isScalarToVector(const SDNode *N) {
return true;
}
/// isDebugLabel - Return true if the specified node represents a debug
/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node).
bool ISD::isDebugLabel(const SDNode *N) {
SDValue Zero;
if (N->getOpcode() == ISD::DBG_LABEL)
return true;
if (N->isMachineOpcode() &&
N->getMachineOpcode() == TargetInstrInfo::DBG_LABEL)
return true;
return false;
}
/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X)
/// when given the operation for (X op Y).
ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) {
@ -503,7 +490,6 @@ static bool doNotCSE(SDNode *N) {
switch (N->getOpcode()) {
default: break;
case ISD::HANDLENODE:
case ISD::DBG_LABEL:
case ISD::EH_LABEL:
return true; // Never CSE these nodes.
}
@ -5438,7 +5424,6 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::UNDEF: return "undef";
case ISD::MERGE_VALUES: return "merge_values";
case ISD::INLINEASM: return "inlineasm";
case ISD::DBG_LABEL: return "dbg_label";
case ISD::EH_LABEL: return "eh_label";
case ISD::HANDLENODE: return "handlenode";
@ -5572,9 +5557,6 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::CTTZ: return "cttz";
case ISD::CTLZ: return "ctlz";
// Debug info
case ISD::DEBUG_LOC: return "debug_loc";
// Trampolines
case ISD::TRAMPOLINE: return "trampoline";

5
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -532,11 +532,6 @@ TargetLowering::TargetLowering(TargetMachine &tm,TargetLoweringObjectFile *tlof)
InitLibcallNames(LibcallRoutineNames);
InitCmpLibcallCCs(CmpLibcallCCs);
InitLibcallCallingConvs(LibcallCallingConvs);
// Tell Legalize whether the assembler supports DEBUG_LOC.
const MCAsmInfo *TASM = TM.getMCAsmInfo();
if (!TASM || !TASM->hasDotLocAndDotFile())
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
}
TargetLowering::~TargetLowering() {

1
lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -613,7 +613,6 @@ void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
break;
case TargetInstrInfo::IMPLICIT_DEF:
case TargetInstrInfo::KILL:
case ARM::DWARF_LOC:
// Do nothing.
break;
case ARM::CONSTPOOL_ENTRY:

3
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -355,9 +355,6 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
// Support label based line numbers.
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);

6
lib/Target/ARM/ARMInstrInfo.td
View File

@ -584,12 +584,6 @@ PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
[(ARMcallseq_start timm:$amt)]>;
}
def DWARF_LOC :
PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), NoItinerary,
".loc $file, $line, $col",
[(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
// Address computation and loads and stores in PIC mode.
let isNotDuplicable = 1 in {
def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),

3
lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -127,9 +127,6 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM)
setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote);
// We don't have line number support yet.
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
// Not implemented yet.

3
lib/Target/Blackfin/BlackfinISelLowering.cpp
View File

@ -114,9 +114,6 @@ BlackfinTargetLowering::BlackfinTargetLowering(TargetMachine &TM)
// READCYCLECOUNTER needs special type legalization.
setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
// We don't have line number support yet.
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
// Use the default implementation.

3
lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -387,9 +387,6 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
// We cannot sextinreg(i1). Expand to shifts.
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
// Support label based line numbers.
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
// We want to legalize GlobalAddress and ConstantPool nodes into the
// appropriate instructions to materialize the address.
for (unsigned sctype = (unsigned) MVT::i8; sctype < (unsigned) MVT::f128;

8
lib/Target/CellSPU/SPUInstrInfo.td
View File

@ -30,14 +30,6 @@ let hasCtrlDep = 1, Defs = [R1], Uses = [R1] in {
[(callseq_end timm:$amt)]>;
}
//===----------------------------------------------------------------------===//
// DWARF debugging Pseudo Instructions
//===----------------------------------------------------------------------===//
def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
".loc $file, $line, $col",
[(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
//===----------------------------------------------------------------------===//
// Loads:
// NB: The ordering is actually important, since the instruction selection

3
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -132,9 +132,6 @@ MipsTargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::FLOG10, MVT::f32, Expand);
setOperationAction(ISD::FEXP, MVT::f32, Expand);
// We don't have line number support yet.
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
// Use the default for now

3
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -182,9 +182,6 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
// We cannot sextinreg(i1). Expand to shifts.
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
// Support label based line numbers.
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);

9
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -1357,15 +1357,6 @@ def RLWNM : MForm_2<23,
}
//===----------------------------------------------------------------------===//
// DWARF Pseudo Instructions
//
def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
"${:comment} .loc $file, $line, $col",
[(dwarf_loc (i32 imm:$line), (i32 imm:$col),
(i32 imm:$file))]>;
//===----------------------------------------------------------------------===//
// PowerPC Instruction Patterns
//

4
lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -644,9 +644,6 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
// We don't have line number support yet.
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
// VASTART needs to be custom lowered to use the VarArgsFrameIndex.
@ -662,7 +659,6 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
// No debug info support yet.
setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
setStackPointerRegisterToSaveRestore(SP::O6);

1
lib/Target/X86/X86CodeEmitter.cpp
View File

@ -595,7 +595,6 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
break;
case TargetInstrInfo::IMPLICIT_DEF:
case TargetInstrInfo::KILL:
case X86::DWARF_LOC:
case X86::FP_REG_KILL:
break;
case X86::MOVPC32r: {

1
lib/Target/X86/X86ISelLowering.cpp
View File

@ -377,7 +377,6 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
if (!Subtarget->isTargetDarwin() &&
!Subtarget->isTargetELF() &&
!Subtarget->isTargetCygMing()) {
setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
}

1
lib/Target/X86/X86InstrInfo.cpp
View File

@ -3133,7 +3133,6 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
break;
case TargetInstrInfo::IMPLICIT_DEF:
case TargetInstrInfo::KILL:
case X86::DWARF_LOC:
case X86::FP_REG_KILL:
break;
case X86::MOVPC32r: {

10
lib/Target/X86/X86InstrInfo.td
View File

@ -3505,16 +3505,6 @@ def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
"movl\t%fs:$src, $dst",
[(set GR32:$dst, (fsload addr:$src))]>, SegFS;
//===----------------------------------------------------------------------===//
// DWARF Pseudo Instructions
//
def DWARF_LOC : I<0, Pseudo, (outs),
(ins i32imm:$line, i32imm:$col, i32imm:$file),
".loc\t$file $line $col",
[(dwarf_loc (i32 imm:$line), (i32 imm:$col),
(i32 imm:$file))]>;
//===----------------------------------------------------------------------===//
// EH Pseudo Instructions
//

3
lib/Target/XCore/XCoreISelLowering.cpp
View File

@ -142,9 +142,6 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
// Debug
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
maxStoresPerMemset = 4;
maxStoresPerMemmove = maxStoresPerMemcpy = 2;

1
utils/TableGen/DAGISelEmitter.cpp
View File

@ -1947,7 +1947,6 @@ void DAGISelEmitter::EmitInstructionSelector(raw_ostream &OS) {
<< " return NULL;\n"
<< " }\n"
<< " case ISD::INLINEASM: return Select_INLINEASM(N);\n"
<< " case ISD::DBG_LABEL: return Select_DBG_LABEL(N);\n"
<< " case ISD::EH_LABEL: return Select_EH_LABEL(N);\n"
<< " case ISD::UNDEF: return Select_UNDEF(N);\n";