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[AMDGPU] Stop using MCRegisterClass::getSize()

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Differential Review: https://reviews.llvm.org/D24675


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284619 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek 2016-10-19 17:40:36 +00:00
parent 740d871c3e
commit 735fbf86f3
4 changed files with 46 additions and 11 deletions
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14
lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
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@ -403,10 +403,10 @@ void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
const MCInstrDesc &Desc = MII.get(MI->getOpcode());
int RCID = Desc.OpInfo[OpNo].RegClass;
if (RCID != -1) {
const MCRegisterClass &ImmRC = MRI.getRegClass(RCID);
if (ImmRC.getSize() == 4)
unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
if (RCBits == 32)
printImmediate32(Op.getImm(), O);
else if (ImmRC.getSize() == 8)
else if (RCBits == 64)
printImmediate64(Op.getImm(), O);
else
llvm_unreachable("Invalid register class size");
@ -424,11 +424,11 @@ void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
O << "0.0";
else {
const MCInstrDesc &Desc = MII.get(MI->getOpcode());
const MCRegisterClass &ImmRC = MRI.getRegClass(Desc.OpInfo[OpNo].RegClass);
if (ImmRC.getSize() == 4)
int RCID = Desc.OpInfo[OpNo].RegClass;
unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
if (RCBits == 32)
printImmediate32(FloatToBits(Op.getFPImm()), O);
else if (ImmRC.getSize() == 8)
else if (RCBits == 64)
printImmediate64(DoubleToBits(Op.getFPImm()), O);
else
llvm_unreachable("Invalid register class size");

2
lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
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@ -214,7 +214,7 @@ void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
// Is this operand a literal immediate?
const MCOperand &Op = MI.getOperand(i);
if (getLitEncoding(Op, RC.getSize(), STI) != 255)
if (getLitEncoding(Op, AMDGPU::getRegBitWidth(RC) / 8, STI) != 255)
continue;
// Yes! Encode it

37
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
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@ -337,11 +337,42 @@ bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
OpType == AMDGPU::OPERAND_REG_INLINE_C_FP;
}
// Avoid using MCRegisterClass::getSize, since that function will go away
// (move from MC* level to Target* level). Return size in bits.
unsigned getRegBitWidth(const MCRegisterClass &RC) {
switch (RC.getID()) {
case AMDGPU::SGPR_32RegClassID:
case AMDGPU::VGPR_32RegClassID:
case AMDGPU::VS_32RegClassID:
case AMDGPU::SReg_32RegClassID:
case AMDGPU::SReg_32_XM0RegClassID:
return 32;
case AMDGPU::SGPR_64RegClassID:
case AMDGPU::VS_64RegClassID:
case AMDGPU::SReg_64RegClassID:
case AMDGPU::VReg_64RegClassID:
return 64;
case AMDGPU::VReg_96RegClassID:
return 96;
case AMDGPU::SGPR_128RegClassID:
case AMDGPU::SReg_128RegClassID:
case AMDGPU::VReg_128RegClassID:
return 128;
case AMDGPU::SReg_256RegClassID:
case AMDGPU::VReg_256RegClassID:
return 256;
case AMDGPU::SReg_512RegClassID:
case AMDGPU::VReg_512RegClassID:
return 512;
default:
llvm_unreachable("Unexpected register class");
}
}
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
unsigned OpNo) {
int RCID = Desc.OpInfo[OpNo].RegClass;
const MCRegisterClass &RC = MRI->getRegClass(RCID);
return RC.getSize();
unsigned RCID = Desc.OpInfo[OpNo].RegClass;
return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
}
bool isInlinableLiteral64(int64_t Literal, bool IsVI) {

4
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
View File

@ -24,6 +24,7 @@ class Function;
class GlobalValue;
class MCContext;
class MCInstrDesc;
class MCRegisterClass;
class MCRegisterInfo;
class MCSection;
class MCSubtargetInfo;
@ -152,6 +153,9 @@ bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
/// \brief Does this opearnd support only inlinable literals?
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
/// \brief Get the size in bits of a register from the register class \p RC.
unsigned getRegBitWidth(const MCRegisterClass &RC);
/// \brief Get size of register operand
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
unsigned OpNo);