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[RDF] Correctly calculate lane masks for defs

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301700 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek 2017-04-28 21:57:53 +00:00
parent 013513893f
commit 737d3b6aab
2 changed files with 59 additions and 2 deletions
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9
lib/Target/Hexagon/RDFLiveness.cpp
View File

@ -759,8 +759,13 @@ void Liveness::computeLiveIns() {
// all related shadows as a single use cluster.
RegisterRef S(RS.first, P.second);
NodeList Ds = getAllReachingDefs(S, PUA, true, false, NoRegs);
for (NodeAddr<DefNode*> D : Ds)
LOX[S.Reg].insert({D.Id, S.Mask});
for (NodeAddr<DefNode*> D : Ds) {
// Calculate the mask corresponding to the visited def.
RegisterAggr TA(PRI);
TA.insert(D.Addr->getRegRef(DFG)).intersect(S);
LaneBitmask TM = TA.makeRegRef().Mask;
LOX[S.Reg].insert({D.Id, TM});
}
}
}

52
test/CodeGen/Hexagon/rdf-def-mask.ll Normal file
View File

@ -0,0 +1,52 @@
; RUN: llc -march=hexagon -O3 -verify-machineinstrs < %s | FileCheck %s
; REQUIRES: asserts
; Check for sane output. This testcase used to crash.
; CHECK: jumpr r31
target triple = "hexagon"
@g0 = external hidden unnamed_addr constant [9 x i16], align 8
; Function Attrs: nounwind readnone
define i64 @fred(i32 %a0) local_unnamed_addr #0 {
b1:
%v2 = icmp slt i32 %a0, 1
br i1 %v2, label %b26, label %b3
b3: ; preds = %b1
%v4 = tail call i32 @llvm.hexagon.S2.clb(i32 %a0)
%v5 = add nsw i32 %v4, -12
%v6 = add nsw i32 %v4, -28
%v7 = tail call i32 @llvm.hexagon.S2.asl.r.r(i32 %a0, i32 %v6)
%v8 = add nsw i32 %v7, -8
%v9 = tail call i32 @llvm.hexagon.S2.asl.r.r(i32 %a0, i32 %v5)
%v10 = getelementptr inbounds [9 x i16], [9 x i16]* @g0, i32 0, i32 %v8
%v11 = load i16, i16* %v10, align 2
%v12 = sext i16 %v11 to i32
%v13 = shl nsw i32 %v12, 16
%v14 = add nsw i32 %v7, -7
%v15 = getelementptr inbounds [9 x i16], [9 x i16]* @g0, i32 0, i32 %v14
%v16 = load i16, i16* %v15, align 2
%v17 = sub i16 %v11, %v16
%v18 = and i32 %v9, 65535
%v19 = zext i16 %v17 to i32
%v20 = tail call i32 @llvm.hexagon.M2.mpyu.nac.ll.s0(i32 %v13, i32 %v18, i32 %v19) #1
%v21 = add nsw i32 %v4, -32
%v22 = zext i32 %v21 to i64
%v23 = shl nuw i64 %v22, 32
%v24 = zext i32 %v20 to i64
%v25 = or i64 %v23, %v24
br label %b26
b26: ; preds = %b3, %b1
%v27 = phi i64 [ %v25, %b3 ], [ 2147483648, %b1 ]
ret i64 %v27
}
declare i32 @llvm.hexagon.S2.clb(i32) #1
declare i32 @llvm.hexagon.S2.asl.r.r(i32, i32) #1
declare i32 @llvm.hexagon.M2.mpyu.nac.ll.s0(i32, i32, i32) #1
attributes #0 = { nounwind readnone "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" }
attributes #1 = { nounwind readnone }