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AMDGPU/SI: select S_ABS_I32 when possible (v2)
v2: added more tests, moved the SALU->VALU conversion to a separate function It looks like it's not possible to get subregisters in the S_ABS lowering code, and I don't feel like guessing without testing what the correct code would look like. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254095 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Marek Olsak
parent
2aff4b612e
commit
73f0848ca2
@ -2412,6 +2412,11 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
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}
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break;
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case AMDGPU::S_ABS_I32:
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lowerScalarAbs(Worklist, Inst);
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Inst->eraseFromParent();
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continue;
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case AMDGPU::S_BFE_U64:
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case AMDGPU::S_BFM_B64:
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llvm_unreachable("Moving this op to VALU not implemented");
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@ -2497,6 +2502,30 @@ const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
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return &AMDGPU::VGPR_32RegClass;
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}
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void SIInstrInfo::lowerScalarAbs(SmallVectorImpl<MachineInstr *> &Worklist,
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MachineInstr *Inst) const {
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MachineBasicBlock &MBB = *Inst->getParent();
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MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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MachineBasicBlock::iterator MII = Inst;
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DebugLoc DL = Inst->getDebugLoc();
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MachineOperand &Dest = Inst->getOperand(0);
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MachineOperand &Src = Inst->getOperand(1);
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unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
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unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
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BuildMI(MBB, MII, DL, get(AMDGPU::V_SUB_I32_e32), TmpReg)
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.addImm(0)
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.addReg(Src.getReg());
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BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg)
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.addReg(Src.getReg())
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.addReg(TmpReg);
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MRI.replaceRegWith(Dest.getReg(), ResultReg);
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addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
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}
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void SIInstrInfo::splitScalar64BitUnaryOp(
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SmallVectorImpl<MachineInstr *> &Worklist,
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MachineInstr *Inst,
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@ -41,6 +41,9 @@ private:
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void swapOperands(MachineBasicBlock::iterator Inst) const;
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void lowerScalarAbs(SmallVectorImpl<MachineInstr *> &Worklist,
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MachineInstr *Inst) const;
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void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
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MachineInstr *Inst, unsigned Opcode) const;
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@ -2174,6 +2174,11 @@ def : Pat <
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(S_MOV_B32 0), sub1))
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>;
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def : Pat <
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(i32 (smax i32:$x, (i32 (ineg i32:$x)))),
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(S_ABS_I32 $x)
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>;
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//===----------------------------------------------------------------------===//
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// SOP2 Patterns
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//===----------------------------------------------------------------------===//
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@ -8,9 +8,7 @@ declare i32 @llvm.AMDGPU.abs(i32) nounwind readnone
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declare i32 @llvm.AMDIL.abs.i32(i32) nounwind readnone
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; FUNC-LABEL: {{^}}s_abs_i32:
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; SI: s_sub_i32
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; SI: s_max_i32
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; SI: s_endpgm
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; SI: s_abs_i32
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; EG: SUB_INT
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; EG: MAX_INT
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156
test/CodeGen/AMDGPU/sminmax.ll
Normal file
156
test/CodeGen/AMDGPU/sminmax.ll
Normal file
@ -0,0 +1,156 @@
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; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}s_abs_i32:
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; GCN: s_abs_i32
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; GCN: s_add_i32
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define void @s_abs_i32(i32 addrspace(1)* %out, i32 %val) nounwind {
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%neg = sub i32 0, %val
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%cond = icmp sgt i32 %val, %neg
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%res = select i1 %cond, i32 %val, i32 %neg
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%res2 = add i32 %res, 2
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store i32 %res2, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_abs_i32:
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; GCN: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SRC:v[0-9]+]]
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; GCN: v_max_i32_e32 {{v[0-9]+}}, [[NEG]], [[SRC]]
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; GCN: v_add_i32
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define void @v_abs_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %src) nounwind {
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%val = load i32, i32 addrspace(1)* %src, align 4
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%neg = sub i32 0, %val
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%cond = icmp sgt i32 %val, %neg
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%res = select i1 %cond, i32 %val, i32 %neg
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%res2 = add i32 %res, 2
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store i32 %res2, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}s_abs_v2i32:
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; TODO: this should use s_abs_i32
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; GCNX: s_abs_i32
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; GCNX: s_abs_i32
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; GCN: s_sub
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; GCN: s_sub
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; GCN-DAG: v_cmp_gt
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; GCN-DAG: v_cmp_gt
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; GCN-DAG: v_cndmask_b32
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; GCN-DAG: v_cndmask_b32
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; GCN: v_add_i32
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; GCN: v_add_i32
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define void @s_abs_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %val) nounwind {
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%z0 = insertelement <2 x i32> undef, i32 0, i32 0
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%z1 = insertelement <2 x i32> %z0, i32 0, i32 1
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%t0 = insertelement <2 x i32> undef, i32 2, i32 0
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%t1 = insertelement <2 x i32> %t0, i32 2, i32 1
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%neg = sub <2 x i32> %z1, %val
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%cond = icmp sgt <2 x i32> %val, %neg
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%res = select <2 x i1> %cond, <2 x i32> %val, <2 x i32> %neg
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%res2 = add <2 x i32> %res, %t1
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store <2 x i32> %res2, <2 x i32> addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_abs_v2i32:
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; GCN: v_sub_i32_e32 [[NEG0:v[0-9]+]], vcc, 0, [[SRC0:v[0-9]+]]
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; GCN: v_sub_i32_e32 [[NEG1:v[0-9]+]], vcc, 0, [[SRC1:v[0-9]+]]
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; TODO: this should use v_max_i32
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; GCNX: v_max_i32_e32 {{v[0-9]+}}, [[NEG0]], [[SRC0]]
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; GCNX: v_max_i32_e32 {{v[0-9]+}}, [[NEG1]], [[SRC1]]
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; GCN-DAG: v_cmp_gt
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; GCN-DAG: v_cmp_gt
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; GCN-DAG: v_cndmask_b32
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; GCN-DAG: v_cndmask_b32
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; GCN: v_add_i32
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; GCN: v_add_i32
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define void @v_abs_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %src) nounwind {
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%z0 = insertelement <2 x i32> undef, i32 0, i32 0
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%z1 = insertelement <2 x i32> %z0, i32 0, i32 1
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%t0 = insertelement <2 x i32> undef, i32 2, i32 0
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%t1 = insertelement <2 x i32> %t0, i32 2, i32 1
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%val = load <2 x i32>, <2 x i32> addrspace(1)* %src, align 4
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%neg = sub <2 x i32> %z1, %val
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%cond = icmp sgt <2 x i32> %val, %neg
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%res = select <2 x i1> %cond, <2 x i32> %val, <2 x i32> %neg
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%res2 = add <2 x i32> %res, %t1
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store <2 x i32> %res2, <2 x i32> addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}s_abs_v4i32:
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; TODO: this should use s_abs_i32
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; GCNX: s_abs_i32
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; GCNX: s_abs_i32
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; GCNX: s_abs_i32
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; GCNX: s_abs_i32
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; GCN: s_sub
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; GCN: s_sub
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; GCN: s_sub
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; GCN: s_sub
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; GCN-DAG: v_cmp_gt
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; GCN-DAG: v_cmp_gt
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; GCN-DAG: v_cmp_gt
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; GCN-DAG: v_cmp_gt
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; GCN-DAG: v_cndmask_b32
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; GCN-DAG: v_cndmask_b32
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; GCN-DAG: v_cndmask_b32
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; GCN-DAG: v_cndmask_b32
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; GCN: v_add_i32
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; GCN: v_add_i32
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define void @s_abs_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %val) nounwind {
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%z0 = insertelement <4 x i32> undef, i32 0, i32 0
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%z1 = insertelement <4 x i32> %z0, i32 0, i32 1
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%z2 = insertelement <4 x i32> %z1, i32 0, i32 2
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%z3 = insertelement <4 x i32> %z2, i32 0, i32 3
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%t0 = insertelement <4 x i32> undef, i32 2, i32 0
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%t1 = insertelement <4 x i32> %t0, i32 2, i32 1
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%t2 = insertelement <4 x i32> %t1, i32 2, i32 2
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%t3 = insertelement <4 x i32> %t2, i32 2, i32 3
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%neg = sub <4 x i32> %z3, %val
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%cond = icmp sgt <4 x i32> %val, %neg
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%res = select <4 x i1> %cond, <4 x i32> %val, <4 x i32> %neg
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%res2 = add <4 x i32> %res, %t3
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store <4 x i32> %res2, <4 x i32> addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_abs_v4i32:
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; GCN: v_sub_i32_e32 [[NEG0:v[0-9]+]], vcc, 0, [[SRC0:v[0-9]+]]
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; GCN: v_sub_i32_e32 [[NEG1:v[0-9]+]], vcc, 0, [[SRC1:v[0-9]+]]
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; GCN: v_sub_i32_e32 [[NEG2:v[0-9]+]], vcc, 0, [[SRC2:v[0-9]+]]
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; GCN: v_sub_i32_e32 [[NEG3:v[0-9]+]], vcc, 0, [[SRC3:v[0-9]+]]
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; TODO: this should use v_max_i32
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; GCNX: v_max_i32_e32 {{v[0-9]+}}, [[NEG0]], [[SRC0]]
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; GCNX: v_max_i32_e32 {{v[0-9]+}}, [[NEG1]], [[SRC1]]
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; GCNX: v_max_i32_e32 {{v[0-9]+}}, [[NEG2]], [[SRC2]]
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; GCNX: v_max_i32_e32 {{v[0-9]+}}, [[NEG3]], [[SRC3]]
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; GCN-DAG: v_cmp_gt
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; GCN-DAG: v_cmp_gt
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; GCN-DAG: v_cmp_gt
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; GCN-DAG: v_cmp_gt
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; GCN-DAG: v_cndmask_b32
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; GCN-DAG: v_cndmask_b32
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; GCN-DAG: v_cndmask_b32
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; GCN-DAG: v_cndmask_b32
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; GCN: v_add_i32
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; GCN: v_add_i32
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; GCN: v_add_i32
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; GCN: v_add_i32
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define void @v_abs_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %src) nounwind {
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%z0 = insertelement <4 x i32> undef, i32 0, i32 0
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%z1 = insertelement <4 x i32> %z0, i32 0, i32 1
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%z2 = insertelement <4 x i32> %z1, i32 0, i32 2
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%z3 = insertelement <4 x i32> %z2, i32 0, i32 3
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%t0 = insertelement <4 x i32> undef, i32 2, i32 0
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%t1 = insertelement <4 x i32> %t0, i32 2, i32 1
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%t2 = insertelement <4 x i32> %t1, i32 2, i32 2
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%t3 = insertelement <4 x i32> %t2, i32 2, i32 3
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%val = load <4 x i32>, <4 x i32> addrspace(1)* %src, align 4
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%neg = sub <4 x i32> %z3, %val
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%cond = icmp sgt <4 x i32> %val, %neg
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%res = select <4 x i1> %cond, <4 x i32> %val, <4 x i32> %neg
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%res2 = add <4 x i32> %res, %t3
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store <4 x i32> %res2, <4 x i32> addrspace(1)* %out, align 4
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ret void
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}
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