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Multiplication support for MMX.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35118 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2007-03-15 21:24:36 +00:00
parent 56fdd7af88
commit 74027e98f1
4 changed files with 34 additions and 1 deletions
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8
include/llvm/IntrinsicsX86.td
View File

@ -576,4 +576,12 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_mmx_psubus_w : GCCBuiltin<"__builtin_ia32_psubusw">,
Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
llvm_v4i16_ty], [IntrNoMem]>;
// Multiplication
def int_x86_mmx_pmulh_w : GCCBuiltin<"__builtin_ia32_pmulhw">,
Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
llvm_v4i16_ty], [IntrNoMem]>;
def int_x86_mmx_pmadd_wd : GCCBuiltin<"__builtin_ia32_pmaddwd">,
Intrinsic<[llvm_v2i32_ty, llvm_v4i16_ty,
llvm_v4i16_ty], [IntrNoMem]>;
}

3
lib/Target/X86/X86ISelLowering.cpp
View File

@ -325,6 +325,9 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
setOperationAction(ISD::SUB, MVT::v4i16, Legal);
setOperationAction(ISD::SUB, MVT::v2i32, Legal);
setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
setOperationAction(ISD::MUL, MVT::v4i16, Legal);
setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32);
setOperationAction(ISD::LOAD, MVT::v4i16, Promote);

7
lib/Target/X86/X86InstrMMX.td
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@ -111,6 +111,11 @@ defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>;
defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw" , int_x86_mmx_pmulh_w , 1>;
defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
// Move Instructions
def MOVD64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
"movd {$src, $dst|$dst, $src}", []>;
@ -139,7 +144,7 @@ def CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
"cvtpi2pd {$src, $dst|$dst, $src}", []>;
def CVTTPS2PIrr: I<0x2C, MRMSrcReg, (ops VR64:$dst, VR128:$src),
"cvttps2pi {$src, $dst|$dst, $src}", []>, TB,
Requires<[HasSSE2]>;
Requires<[HasMMX]>;
def CVTTPS2PIrm: I<0x2C, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
"cvttps2pi {$src, $dst|$dst, $src}", []>, TB,
Requires<[HasMMX]>;

17
test/CodeGen/X86/mmx-arith.ll
View File

@ -23,6 +23,9 @@ entry:
%tmp89 = load <8 x i8>* %B ; <<8 x i8>> [#uses=1]
%tmp105 = tail call <8 x i8> @llvm.x86.mmx.psubus.b( <8 x i8> %tmp80, <8 x i8> %tmp89 ) ; <<8 x i8>> [#uses=1]
store <8 x i8> %tmp105, <8 x i8>* %A
%tmp13 = load <8 x i8>* %A ; <<8 x i8>> [#uses=1]
%tmp16 = mul <8 x i8> %tmp13, %tmp105 ; <<8 x i8>> [#uses=1]
store <8 x i8> %tmp16, <8 x i8>* %B
tail call void @llvm.x86.mmx.emms( )
ret void
}
@ -36,6 +39,9 @@ entry:
%tmp9 = load <2 x i32>* %B ; <<2 x i32>> [#uses=1]
%tmp10 = sub <2 x i32> %tmp4, %tmp9 ; <<2 x i32>> [#uses=1]
store <2 x i32> %tmp10, <2 x i32>* %B
%tmp13 = load <2 x i32>* %A ; <<2 x i32>> [#uses=1]
%tmp16 = mul <2 x i32> %tmp13, %tmp10 ; <<2 x i32>> [#uses=1]
store <2 x i32> %tmp16, <2 x i32>* %B
tail call void @llvm.x86.mmx.emms( )
ret void
}
@ -61,6 +67,13 @@ entry:
%tmp89 = load <4 x i16>* %B ; <<4 x i16>> [#uses=1]
%tmp105 = tail call <4 x i16> @llvm.x86.mmx.psubus.w( <4 x i16> %tmp80, <4 x i16> %tmp89 ) ; <<4 x i16>> [#uses=1]
store <4 x i16> %tmp105, <4 x i16>* %A
%tmp22 = load <4 x i16>* %A ; <<4 x i16>> [#uses=1]
%tmp24 = tail call <4 x i16> @llvm.x86.mmx.pmulh.w( <4 x i16> %tmp22, <4 x i16> %tmp105 ) ; <<4 x i16>> [#uses=2]
store <4 x i16> %tmp24, <4 x i16>* %A
%tmp28 = load <4 x i16>* %B ; <<4 x i16>> [#uses=1]
%tmp33 = tail call <2 x i32> @llvm.x86.mmx.pmadd.wd( <4 x i16> %tmp24, <4 x i16> %tmp28 ) ; <<2 x i32>> [#uses=1]
%tmp34 = bitcast <2 x i32> %tmp33 to <4 x i16> ; <<4 x i16>> [#uses=1]
store <4 x i16> %tmp34, <4 x i16>* %A
tail call void @llvm.x86.mmx.emms( )
ret void
}
@ -81,4 +94,8 @@ declare <8 x i8> @llvm.x86.mmx.psubs.b(<8 x i8>, <8 x i8>)
declare <8 x i8> @llvm.x86.mmx.psubus.b(<8 x i8>, <8 x i8>)
declare <4 x i16> @llvm.x86.mmx.pmulh.w(<4 x i16>, <4 x i16>)
declare <2 x i32> @llvm.x86.mmx.pmadd.wd(<4 x i16>, <4 x i16>)
declare void @llvm.x86.mmx.emms()