From 7417e353113ab169ba6bc7616c932a6f960621e2 Mon Sep 17 00:00:00 2001
From: Strahinja Petrovic <strahinja.petrovic@rt-rk.com>
Date: Mon, 13 Jun 2016 10:29:29 +0000
Subject: [PATCH] This patch fixes handling long double type when it is
 constant in soft float mode on PowerPC 32 architecture.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272543 91177308-0d34-0410-b5e6-96231b3b80d8
---
 .../SelectionDAG/LegalizeFloatTypes.cpp       | 23 +++++++++++++++---
 .../PowerPC/ppc32-constant-BE-ppcf128.ll      | 24 +++++++++++++++++++
 2 files changed, 44 insertions(+), 3 deletions(-)
 create mode 100644 test/CodeGen/PowerPC/ppc32-constant-BE-ppcf128.ll

diff --git a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 81d070bb719..47dc0a4ceae 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -149,9 +149,26 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(SDNode *N, unsigned ResNo) {
   if (isLegalInHWReg(N->getValueType(ResNo)))
     return SDValue(N, ResNo);
   ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
-  return DAG.getConstant(CN->getValueAPF().bitcastToAPInt(), SDLoc(CN),
-                         TLI.getTypeToTransformTo(*DAG.getContext(),
-                                                  CN->getValueType(0)));
+  // In ppcf128, the high 64 bits are always first in memory regardless
+  // of Endianness. LLVM's APFloat representation is not Endian sensitive,
+  // and so always converts into a 128-bit APInt in a non-Endian-sensitive
+  // way. However, APInt's are serialized in an Endian-sensitive fashion,
+  // so on big-Endian targets, the two doubles are output in the wrong 
+  // order. Fix this by manually flipping the order of the high 64 bits
+  // and the low 64 bits here.
+  if (DAG.getDataLayout().isBigEndian() &&
+      CN->getValueType(0).getSimpleVT() == llvm::MVT::ppcf128) {
+    uint64_t words[2] = { CN->getValueAPF().bitcastToAPInt().getRawData()[1],
+                          CN->getValueAPF().bitcastToAPInt().getRawData()[0] };
+    APInt Val(128, words);
+    return DAG.getConstant(Val, SDLoc(CN),
+                           TLI.getTypeToTransformTo(*DAG.getContext(),
+                                                    CN->getValueType(0)));
+  } else {
+    return DAG.getConstant(CN->getValueAPF().bitcastToAPInt(), SDLoc(CN),
+                           TLI.getTypeToTransformTo(*DAG.getContext(),
+                                                    CN->getValueType(0)));
+  }
 }
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N) {
diff --git a/test/CodeGen/PowerPC/ppc32-constant-BE-ppcf128.ll b/test/CodeGen/PowerPC/ppc32-constant-BE-ppcf128.ll
new file mode 100644
index 00000000000..3a23ae31a85
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppc32-constant-BE-ppcf128.ll
@@ -0,0 +1,24 @@
+; RUN: llc -O2 -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s
+
+target datalayout = "E-m:e-p:32:32-i64:64-n32"
+target triple = "powerpc-buildroot-linux-gnu"
+
+@.str = private unnamed_addr constant [5 x i8] c"%Lf\0A\00", align 1
+
+define i32 @main() #0 {
+entry:
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), ppc_fp128 0xM3FF00000000000000000000000000000)
+  ret i32 0
+}
+
+; First available register for long double argument is r4, so put
+; Hi part in r4/r5, Lo part in r6/r7 (do not switch Hi/Lo parts)
+; CHECK: lis 4, 16368
+; CHECK-NOT: lis 6, 16368
+; CHECK: li 5, 0
+; CHECK: li 7, 0
+
+declare i32 @printf(i8* nocapture readonly, ...)
+
+attributes #0 = { "use-soft-float"="true" }
+