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Remove TargetInstrInfo::copyRegToReg entirely.

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Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no
longer a default implementation forwarding to copyRegToReg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108095 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2010-07-11 17:01:17 +00:00
parent d6d7abaf4e
commit 744b3a5acd
6 changed files with 9 additions and 41 deletions
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3
docs/WritingAnLLVMBackend.html
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@ -1310,7 +1310,8 @@ implementation in <tt>SparcInstrInfo.cpp</tt>:
a direct store to a stack slot, return the register number of the
destination and the <tt>FrameIndex</tt> of the stack slot.</li>
<li><tt>copyRegToReg</tt> &mdash; Copy values between a pair of registers.</li>
<li><tt>copyPhysReg</tt> &mdash; Copy values between a pair of physical
registers.</li>
<li><tt>storeRegToStackSlot</tt> &mdash; Store a register value to a stack
slot.</li>

20
include/llvm/Target/TargetInstrInfo.h
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@ -357,7 +357,9 @@ public:
virtual void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const =0;
bool KillSrc) const {
assert(0 && "Target didn't implement TargetInstrInfo::copyPhysReg!");
}
/// storeRegToStackSlot - Store the specified register of the given register
/// class to the specified stack frame index. The store instruction is to be
@ -648,22 +650,6 @@ public:
virtual ScheduleHazardRecognizer *
CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const;
virtual void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const;
/// copyRegToReg - Legacy hook going away soon. Targets should implement
/// copyPhysReg instead.
virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC,
DebugLoc DL) const {
assert(0 && "Target didn't implement TargetInstrInfo::copyPhysReg!");
return false;
}
};
} // End llvm namespace

3
include/llvm/Target/TargetOpcodes.h
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@ -62,8 +62,7 @@ namespace TargetOpcode {
/// used between instruction selection and MachineInstr creation, before
/// virtual registers have been created for all the instructions, and it's
/// only needed in cases where the register classes implied by the
/// instructions are insufficient. The actual MachineInstrs to perform
/// the copy are emitted with the TargetInstrInfo::copyRegToReg hook.
/// instructions are insufficient. It is emitted as a COPY MachineInstr.
COPY_TO_REGCLASS = 10,
/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic

17
lib/CodeGen/TargetInstrInfoImpl.cpp
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@ -438,20 +438,3 @@ ScheduleHazardRecognizer *TargetInstrInfoImpl::
CreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const {
return (ScheduleHazardRecognizer *)new PostRAHazardRecognizer(II);
}
// Default implementation of copyPhysReg using copyRegToReg.
void TargetInstrInfoImpl::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const {
assert(TargetRegisterInfo::isPhysicalRegister(DestReg));
assert(TargetRegisterInfo::isPhysicalRegister(SrcReg));
const TargetRegisterInfo *TRI = MBB.getParent()->getTarget().getRegisterInfo();
const TargetRegisterClass *DRC = TRI->getPhysicalRegisterRegClass(DestReg);
const TargetRegisterClass *SRC = TRI->getPhysicalRegisterRegClass(SrcReg);
if (!copyRegToReg(MBB, MI, DestReg, SrcReg, DRC, SRC, DL))
llvm_unreachable("Cannot emit physreg copy instruction");
if (KillSrc)
llvm::prior(MI)->addRegisterKilled(SrcReg, TRI, true);
}

4
test/CodeGen/Blackfin/cmp64.ll
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@ -1,8 +1,8 @@
; RUN: llc < %s -march=bfin
; This test tries to use a JustCC register as a data operand for MOVEcc. It
; calls copyRegToReg(JustCC -> DP), failing because JustCC can only be copied to
; D. The proper solution would be to restrict the virtual register to D only.
; copies (JustCC -> DP), failing because JustCC can only be copied to D.
; The proper solution would be to restrict the virtual register to D only.
define i32 @main() {
entry:

3
test/TableGen/TargetInstrInfo.td
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@ -83,8 +83,7 @@ class Inst<dag opnds, string asmstr, bits<8> opcode,
// the pattern.
// 6. Address expressions should become first-class entities.
// Simple copy instruction. isMoveInstr could easily be inferred from this,
// as could TargetRegisterInfo::copyRegToReg.
// Simple copy instruction.
def MOV8rr : Inst<(ops R8:$dst, R8:$src),
"mov $dst, $src", 0x88, MRMDestReg,
[(set R8:$dst, R8:$src)]>;