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[AArch64] Prefer Bcc to CBZ/CBNZ/TBZ/TBNZ when NZCV flags can be set for "free".
This patch contains a pass that transforms CBZ/CBNZ/TBZ/TBNZ instructions into a conditional branch (Bcc), when the NZCV flags can be set for "free". This is preferred on targets that have more flexibility when scheduling Bcc instructions as compared to CBZ/CBNZ/TBZ/TBNZ (assuming all other variables are equal). This can reduce register pressure and is also the default behavior for GCC. A few examples: add w8, w0, w1 -> cmn w0, w1 ; CMN is an alias of ADDS. cbz w8, .LBB_2 -> b.eq .LBB0_2 ; single def/use of w8 removed. add w8, w0, w1 -> adds w8, w0, w1 ; w8 has multiple uses. cbz w8, .LBB1_2 -> b.eq .LBB1_2 sub w8, w0, w1 -> subs w8, w0, w1 ; w8 has multiple uses. tbz w8, #31, .LBB6_2 -> b.ge .LBB6_2 In looking at all current sub-target machine descriptions, this transformation appears to be either positive or neutral. Differential Revision: https://reviews.llvm.org/D34220. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306144 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier
parent
2624197bc0
commit
74854f1432
@ -31,6 +31,7 @@ class MachineFunctionPass;
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FunctionPass *createAArch64DeadRegisterDefinitions();
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FunctionPass *createAArch64RedundantCopyEliminationPass();
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FunctionPass *createAArch64CondBrTuning();
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FunctionPass *createAArch64ConditionalCompares();
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FunctionPass *createAArch64AdvSIMDScalar();
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FunctionPass *createAArch64ISelDag(AArch64TargetMachine &TM,
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@ -55,6 +56,7 @@ void initializeAArch64A53Fix835769Pass(PassRegistry&);
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void initializeAArch64A57FPLoadBalancingPass(PassRegistry&);
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void initializeAArch64AdvSIMDScalarPass(PassRegistry&);
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void initializeAArch64CollectLOHPass(PassRegistry&);
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void initializeAArch64CondBrTuningPass(PassRegistry &);
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void initializeAArch64ConditionalComparesPass(PassRegistry&);
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void initializeAArch64ConditionOptimizerPass(PassRegistry&);
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void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry&);
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336
lib/Target/AArch64/AArch64CondBrTuning.cpp
Normal file
336
lib/Target/AArch64/AArch64CondBrTuning.cpp
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@ -0,0 +1,336 @@
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//===-- AArch64CondBrTuning.cpp --- Conditional branch tuning for AArch64 -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file contains a pass that transforms CBZ/CBNZ/TBZ/TBNZ instructions
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/// into a conditional branch (B.cond), when the NZCV flags can be set for
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/// "free". This is preferred on targets that have more flexibility when
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/// scheduling B.cond instructions as compared to CBZ/CBNZ/TBZ/TBNZ (assuming
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/// all other variables are equal). This can also reduce register pressure.
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///
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/// A few examples:
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///
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/// 1) add w8, w0, w1 -> cmn w0, w1 ; CMN is an alias of ADDS.
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/// cbz w8, .LBB_2 -> b.eq .LBB0_2
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///
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/// 2) add w8, w0, w1 -> adds w8, w0, w1 ; w8 has multiple uses.
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/// cbz w8, .LBB1_2 -> b.eq .LBB1_2
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///
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/// 3) sub w8, w0, w1 -> subs w8, w0, w1 ; w8 has multiple uses.
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/// tbz w8, #31, .LBB6_2 -> b.ge .LBB6_2
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///
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "AArch64Subtarget.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineTraceMetrics.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "aarch64-cond-br-tuning"
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#define AARCH64_CONDBR_TUNING_NAME "AArch64 Conditional Branch Tuning"
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namespace {
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class AArch64CondBrTuning : public MachineFunctionPass {
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const AArch64InstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MachineRegisterInfo *MRI;
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public:
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static char ID;
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AArch64CondBrTuning() : MachineFunctionPass(ID) {
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initializeAArch64CondBrTuningPass(*PassRegistry::getPassRegistry());
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return AARCH64_CONDBR_TUNING_NAME; }
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private:
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MachineInstr *getOperandDef(const MachineOperand &MO);
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MachineInstr *convertToFlagSetting(MachineInstr &MI, bool IsFlagSetting);
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MachineInstr *convertToCondBr(MachineInstr &MI);
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bool tryToTuneBranch(MachineInstr &MI, MachineInstr &DefMI);
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};
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} // end anonymous namespace
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char AArch64CondBrTuning::ID = 0;
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INITIALIZE_PASS(AArch64CondBrTuning, "aarch64-cond-br-tuning",
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AARCH64_CONDBR_TUNING_NAME, false, false)
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void AArch64CondBrTuning::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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MachineInstr *AArch64CondBrTuning::getOperandDef(const MachineOperand &MO) {
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if (!TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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return nullptr;
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return MRI->getUniqueVRegDef(MO.getReg());
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}
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MachineInstr *AArch64CondBrTuning::convertToFlagSetting(MachineInstr &MI,
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bool IsFlagSetting) {
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// If this is already the flag setting version of the instruction (e.g., SUBS)
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// just make sure the implicit-def of NZCV isn't marked dead.
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if (IsFlagSetting) {
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for (unsigned I = MI.getNumExplicitOperands(), E = MI.getNumOperands();
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I != E; ++I) {
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MachineOperand &MO = MI.getOperand(I);
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if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV)
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MO.setIsDead(false);
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}
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return &MI;
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}
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bool Is64Bit;
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unsigned NewOpc = TII->convertToFlagSettingOpc(MI.getOpcode(), Is64Bit);
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unsigned NewDestReg = MI.getOperand(0).getReg();
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if (MRI->hasOneNonDBGUse(MI.getOperand(0).getReg()))
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NewDestReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
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MachineInstrBuilder MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
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TII->get(NewOpc), NewDestReg);
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for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
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MIB.add(MI.getOperand(I));
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return MIB;
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}
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MachineInstr *AArch64CondBrTuning::convertToCondBr(MachineInstr &MI) {
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AArch64CC::CondCode CC;
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MachineBasicBlock *TargetMBB = TII->getBranchDestBlock(MI);
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switch (MI.getOpcode()) {
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default:
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llvm_unreachable("Unexpected opcode!");
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case AArch64::CBZW:
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case AArch64::CBZX:
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CC = AArch64CC::EQ;
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break;
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case AArch64::CBNZW:
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case AArch64::CBNZX:
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CC = AArch64CC::NE;
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break;
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case AArch64::TBZW:
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case AArch64::TBZX:
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CC = AArch64CC::GE;
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break;
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case AArch64::TBNZW:
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case AArch64::TBNZX:
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CC = AArch64CC::LT;
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break;
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}
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return BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(AArch64::Bcc))
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.addImm(CC)
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.addMBB(TargetMBB);
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}
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bool AArch64CondBrTuning::tryToTuneBranch(MachineInstr &MI,
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MachineInstr &DefMI) {
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// We don't want NZCV bits live across blocks.
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if (MI.getParent() != DefMI.getParent())
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return false;
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bool IsFlagSetting = true;
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unsigned MIOpc = MI.getOpcode();
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MachineInstr *NewCmp = nullptr, *NewBr = nullptr;
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switch (DefMI.getOpcode()) {
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default:
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return false;
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case AArch64::ADDWri:
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case AArch64::ADDWrr:
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case AArch64::ADDWrs:
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case AArch64::ADDWrx:
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case AArch64::ANDWri:
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case AArch64::ANDWrr:
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case AArch64::ANDWrs:
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case AArch64::BICWrr:
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case AArch64::BICWrs:
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case AArch64::SUBWri:
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case AArch64::SUBWrr:
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case AArch64::SUBWrs:
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case AArch64::SUBWrx:
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IsFlagSetting = false;
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case AArch64::ADDSWri:
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case AArch64::ADDSWrr:
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case AArch64::ADDSWrs:
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case AArch64::ADDSWrx:
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case AArch64::ANDSWri:
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case AArch64::ANDSWrr:
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case AArch64::ANDSWrs:
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case AArch64::BICSWrr:
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case AArch64::BICSWrs:
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case AArch64::SUBSWri:
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case AArch64::SUBSWrr:
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case AArch64::SUBSWrs:
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case AArch64::SUBSWrx:
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switch (MIOpc) {
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default:
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llvm_unreachable("Unexpected opcode!");
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case AArch64::CBZW:
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case AArch64::CBNZW:
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case AArch64::TBZW:
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case AArch64::TBNZW:
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// Check to see if the TBZ/TBNZ is checking the sign bit.
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if ((MIOpc == AArch64::TBZW || MIOpc == AArch64::TBNZW) &&
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MI.getOperand(1).getImm() != 31)
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return false;
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// There must not be any instruction between DefMI and MI that clobbers or
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// reads NZCV.
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MachineBasicBlock::iterator I(DefMI), E(MI);
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for (I = std::next(I); I != E; ++I) {
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if (I->modifiesRegister(AArch64::NZCV, TRI) ||
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I->readsRegister(AArch64::NZCV, TRI))
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return false;
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}
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DEBUG(dbgs() << " Replacing instructions:\n ");
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DEBUG(DefMI.print(dbgs()));
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DEBUG(dbgs() << " ");
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DEBUG(MI.print(dbgs()));
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NewCmp = convertToFlagSetting(DefMI, IsFlagSetting);
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NewBr = convertToCondBr(MI);
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break;
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}
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break;
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case AArch64::ADDXri:
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case AArch64::ADDXrr:
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case AArch64::ADDXrs:
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case AArch64::ADDXrx:
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case AArch64::ANDXri:
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case AArch64::ANDXrr:
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case AArch64::ANDXrs:
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case AArch64::BICXrr:
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case AArch64::BICXrs:
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case AArch64::SUBXri:
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case AArch64::SUBXrr:
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case AArch64::SUBXrs:
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case AArch64::SUBXrx:
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IsFlagSetting = false;
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case AArch64::ADDSXri:
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case AArch64::ADDSXrr:
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case AArch64::ADDSXrs:
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case AArch64::ADDSXrx:
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case AArch64::ANDSXri:
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case AArch64::ANDSXrr:
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case AArch64::ANDSXrs:
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case AArch64::BICSXrr:
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case AArch64::BICSXrs:
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case AArch64::SUBSXri:
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case AArch64::SUBSXrr:
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case AArch64::SUBSXrs:
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case AArch64::SUBSXrx:
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switch (MIOpc) {
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default:
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llvm_unreachable("Unexpected opcode!");
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case AArch64::CBZX:
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case AArch64::CBNZX:
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case AArch64::TBZX:
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case AArch64::TBNZX: {
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// Check to see if the TBZ/TBNZ is checking the sign bit.
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if ((MIOpc == AArch64::TBZX || MIOpc == AArch64::TBNZX) &&
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MI.getOperand(1).getImm() != 63)
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return false;
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// There must not be any instruction between DefMI and MI that clobbers or
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// reads NZCV.
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MachineBasicBlock::iterator I(DefMI), E(MI);
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for (I = std::next(I); I != E; ++I) {
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if (I->modifiesRegister(AArch64::NZCV, TRI) ||
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I->readsRegister(AArch64::NZCV, TRI))
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return false;
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}
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DEBUG(dbgs() << " Replacing instructions:\n ");
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DEBUG(DefMI.print(dbgs()));
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DEBUG(dbgs() << " ");
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DEBUG(MI.print(dbgs()));
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NewCmp = convertToFlagSetting(DefMI, IsFlagSetting);
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NewBr = convertToCondBr(MI);
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break;
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}
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}
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break;
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}
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assert(NewCmp && NewBr && "Expected new instructions.");
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DEBUG(dbgs() << " with instruction:\n ");
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DEBUG(NewCmp->print(dbgs()));
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DEBUG(dbgs() << " ");
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DEBUG(NewBr->print(dbgs()));
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// If this was a flag setting version of the instruction, we use the original
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// instruction by just clearing the dead marked on the implicit-def of NCZV.
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// Therefore, we should not erase this instruction.
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if (!IsFlagSetting)
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DefMI.eraseFromParent();
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MI.eraseFromParent();
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return true;
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}
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bool AArch64CondBrTuning::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(*MF.getFunction()))
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return false;
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DEBUG(dbgs() << "********** AArch64 Conditional Branch Tuning **********\n"
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<< "********** Function: " << MF.getName() << '\n');
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TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());
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TRI = MF.getSubtarget().getRegisterInfo();
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MRI = &MF.getRegInfo();
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bool Changed = false;
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for (MachineBasicBlock &MBB : MF) {
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bool LocalChange = false;
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for (MachineBasicBlock::iterator I = MBB.getFirstTerminator(),
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E = MBB.end();
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I != E; ++I) {
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MachineInstr &MI = *I;
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switch (MI.getOpcode()) {
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default:
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break;
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case AArch64::CBZW:
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case AArch64::CBZX:
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case AArch64::CBNZW:
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case AArch64::CBNZX:
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case AArch64::TBZW:
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case AArch64::TBZX:
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case AArch64::TBNZW:
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case AArch64::TBNZX:
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MachineInstr *DefMI = getOperandDef(MI.getOperand(0));
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LocalChange = (DefMI && tryToTuneBranch(MI, *DefMI));
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break;
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}
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// If the optimization was successful, we can't optimize any other
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// branches because doing so would clobber the NZCV flags.
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if (LocalChange) {
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Changed = true;
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break;
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}
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}
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}
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return Changed;
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}
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FunctionPass *llvm::createAArch64CondBrTuning() {
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return new AArch64CondBrTuning();
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}
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@ -1036,7 +1036,7 @@ static bool UpdateOperandRegClass(MachineInstr &Instr) {
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/// \brief Return the opcode that does not set flags when possible - otherwise
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/// return the original opcode. The caller is responsible to do the actual
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/// substitution and legality checking.
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static unsigned convertFlagSettingOpcode(const MachineInstr &MI) {
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static unsigned convertToNonFlagSettingOpc(const MachineInstr &MI) {
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// Don't convert all compare instructions, because for some the zero register
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// encoding becomes the sp register.
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bool MIDefinesZeroReg = false;
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@ -1145,7 +1145,7 @@ bool AArch64InstrInfo::optimizeCompareInstr(
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return true;
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}
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unsigned Opc = CmpInstr.getOpcode();
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unsigned NewOpc = convertFlagSettingOpcode(CmpInstr);
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unsigned NewOpc = convertToNonFlagSettingOpc(CmpInstr);
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if (NewOpc == Opc)
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return false;
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const MCInstrDesc &MCID = get(NewOpc);
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@ -3318,7 +3318,7 @@ static bool getMaddPatterns(MachineInstr &Root,
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// When NZCV is live bail out.
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if (Cmp_NZCV == -1)
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return false;
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unsigned NewOpc = convertFlagSettingOpcode(Root);
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unsigned NewOpc = convertToNonFlagSettingOpc(Root);
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// When opcode can't change bail out.
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// CHECKME: do we miss any cases for opcode conversion?
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if (NewOpc == Opc)
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@ -119,6 +119,44 @@ public:
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}
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}
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/// \brief Return the opcode that set flags when possible. The caller is
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/// responsible for ensuring the opc has a flag setting equivalent.
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static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit) {
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switch (Opc) {
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default:
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llvm_unreachable("Opcode has no flag setting equivalent!");
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// 32-bit cases:
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case AArch64::ADDWri: Is64Bit = false; return AArch64::ADDSWri;
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case AArch64::ADDWrr: Is64Bit = false; return AArch64::ADDSWrr;
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case AArch64::ADDWrs: Is64Bit = false; return AArch64::ADDSWrs;
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case AArch64::ADDWrx: Is64Bit = false; return AArch64::ADDSWrx;
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case AArch64::ANDWri: Is64Bit = false; return AArch64::ANDSWri;
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case AArch64::ANDWrr: Is64Bit = false; return AArch64::ANDSWrr;
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case AArch64::ANDWrs: Is64Bit = false; return AArch64::ANDSWrs;
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case AArch64::BICWrr: Is64Bit = false; return AArch64::BICSWrr;
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case AArch64::BICWrs: Is64Bit = false; return AArch64::BICSWrs;
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case AArch64::SUBWri: Is64Bit = false; return AArch64::SUBSWri;
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case AArch64::SUBWrr: Is64Bit = false; return AArch64::SUBSWrr;
|
||||
case AArch64::SUBWrs: Is64Bit = false; return AArch64::SUBSWrs;
|
||||
case AArch64::SUBWrx: Is64Bit = false; return AArch64::SUBSWrx;
|
||||
// 64-bit cases:
|
||||
case AArch64::ADDXri: Is64Bit = true; return AArch64::ADDSXri;
|
||||
case AArch64::ADDXrr: Is64Bit = true; return AArch64::ADDSXrr;
|
||||
case AArch64::ADDXrs: Is64Bit = true; return AArch64::ADDSXrs;
|
||||
case AArch64::ADDXrx: Is64Bit = true; return AArch64::ADDSXrx;
|
||||
case AArch64::ANDXri: Is64Bit = true; return AArch64::ANDSXri;
|
||||
case AArch64::ANDXrr: Is64Bit = true; return AArch64::ANDSXrr;
|
||||
case AArch64::ANDXrs: Is64Bit = true; return AArch64::ANDSXrs;
|
||||
case AArch64::BICXrr: Is64Bit = true; return AArch64::BICSXrr;
|
||||
case AArch64::BICXrs: Is64Bit = true; return AArch64::BICSXrs;
|
||||
case AArch64::SUBXri: Is64Bit = true; return AArch64::SUBSXri;
|
||||
case AArch64::SUBXrr: Is64Bit = true; return AArch64::SUBSXrr;
|
||||
case AArch64::SUBXrs: Is64Bit = true; return AArch64::SUBSXrs;
|
||||
case AArch64::SUBXrx: Is64Bit = true; return AArch64::SUBSXrx;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/// Return true if this is a load/store that can be potentially paired/merged.
|
||||
bool isCandidateToMergeOrPair(MachineInstr &MI) const;
|
||||
|
||||
|
||||
@ -47,6 +47,11 @@ static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
|
||||
cl::desc("Enable the CCMP formation pass"),
|
||||
cl::init(true), cl::Hidden);
|
||||
|
||||
static cl::opt<bool>
|
||||
EnableCondBrTuning("aarch64-enable-cond-br-tune",
|
||||
cl::desc("Enable the conditional branch tuning pass"),
|
||||
cl::init(true), cl::Hidden);
|
||||
|
||||
static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
|
||||
cl::desc("Enable the machine combiner pass"),
|
||||
cl::init(true), cl::Hidden);
|
||||
@ -429,6 +434,8 @@ bool AArch64PassConfig::addILPOpts() {
|
||||
addPass(createAArch64ConditionalCompares());
|
||||
if (EnableMCR)
|
||||
addPass(&MachineCombinerID);
|
||||
if (EnableCondBrTuning)
|
||||
addPass(createAArch64CondBrTuning());
|
||||
if (EnableEarlyIfConversion)
|
||||
addPass(&EarlyIfConverterID);
|
||||
if (EnableStPairSuppress)
|
||||
|
||||
@ -43,6 +43,7 @@ add_llvm_target(AArch64CodeGen
|
||||
AArch64AsmPrinter.cpp
|
||||
AArch64CleanupLocalDynamicTLSPass.cpp
|
||||
AArch64CollectLOH.cpp
|
||||
AArch64CondBrTuning.cpp
|
||||
AArch64ConditionalCompares.cpp
|
||||
AArch64DeadRegisterDefinitionsPass.cpp
|
||||
AArch64ExpandPseudoInsts.cpp
|
||||
|
||||
@ -27,7 +27,7 @@ if.else:
|
||||
do.cond:
|
||||
%max.1 = phi i32 [ %0, %do.body ], [ %max.0, %if.else ]
|
||||
%min.1 = phi i32 [ %min.0, %do.body ], [ %.min.0, %if.else ]
|
||||
; CHECK: cbnz
|
||||
; CHECK: b.ne
|
||||
%dec = add i32 %n.addr.0, -1
|
||||
%tobool = icmp eq i32 %dec, 0
|
||||
br i1 %tobool, label %do.end, label %do.body
|
||||
|
||||
@ -78,9 +78,9 @@ declare i32 @doSomething(i32, i32*)
|
||||
; Next BB.
|
||||
; CHECK: [[LOOP:LBB[0-9_]+]]: ; %for.body
|
||||
; CHECK: bl _something
|
||||
; CHECK-NEXT: sub [[IV]], [[IV]], #1
|
||||
; CHECK-NEXT: subs [[IV]], [[IV]], #1
|
||||
; CHECK-NEXT: add [[SUM]], w0, [[SUM]]
|
||||
; CHECK-NEXT: cbnz [[IV]], [[LOOP]]
|
||||
; CHECK-NEXT: b.ne [[LOOP]]
|
||||
;
|
||||
; Next BB.
|
||||
; Copy SUM into the returned register + << 3.
|
||||
@ -144,9 +144,9 @@ declare i32 @something(...)
|
||||
; Next BB.
|
||||
; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ; %for.body
|
||||
; CHECK: bl _something
|
||||
; CHECK-NEXT: sub [[IV]], [[IV]], #1
|
||||
; CHECK-NEXT: subs [[IV]], [[IV]], #1
|
||||
; CHECK-NEXT: add [[SUM]], w0, [[SUM]]
|
||||
; CHECK-NEXT: cbnz [[IV]], [[LOOP_LABEL]]
|
||||
; CHECK-NEXT: b.ne [[LOOP_LABEL]]
|
||||
; Next BB.
|
||||
; CHECK: ; %for.end
|
||||
; CHECK: mov w0, [[SUM]]
|
||||
@ -188,9 +188,9 @@ for.end: ; preds = %for.body
|
||||
;
|
||||
; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ; %for.body
|
||||
; CHECK: bl _something
|
||||
; CHECK-NEXT: sub [[IV]], [[IV]], #1
|
||||
; CHECK-NEXT: subs [[IV]], [[IV]], #1
|
||||
; CHECK-NEXT: add [[SUM]], w0, [[SUM]]
|
||||
; CHECK-NEXT: cbnz [[IV]], [[LOOP_LABEL]]
|
||||
; CHECK-NEXT: b.ne [[LOOP_LABEL]]
|
||||
; Next BB.
|
||||
; CHECK: bl _somethingElse
|
||||
; CHECK-NEXT: lsl w0, [[SUM]], #3
|
||||
@ -259,9 +259,9 @@ declare void @somethingElse(...)
|
||||
;
|
||||
; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ; %for.body
|
||||
; CHECK: bl _something
|
||||
; CHECK-NEXT: sub [[IV]], [[IV]], #1
|
||||
; CHECK-NEXT: subs [[IV]], [[IV]], #1
|
||||
; CHECK-NEXT: add [[SUM]], w0, [[SUM]]
|
||||
; CHECK-NEXT: cbnz [[IV]], [[LOOP_LABEL]]
|
||||
; CHECK-NEXT: b.ne [[LOOP_LABEL]]
|
||||
; Next BB.
|
||||
; CHECK: lsl w0, [[SUM]], #3
|
||||
;
|
||||
@ -343,9 +343,9 @@ entry:
|
||||
; CHECK-NEXT: add [[NEXT_VA_ADDR:x[0-9]+]], [[VA_ADDR]], #8
|
||||
; CHECK-NEXT: str [[NEXT_VA_ADDR]], [sp, #8]
|
||||
; CHECK-NEXT: ldr [[VA_VAL:w[0-9]+]], {{\[}}[[VA_ADDR]]]
|
||||
; CHECK-NEXT: sub w1, w1, #1
|
||||
; CHECK-NEXT: subs w1, w1, #1
|
||||
; CHECK-NEXT: add [[SUM]], [[SUM]], [[VA_VAL]]
|
||||
; CHECK-NEXT: cbnz w1, [[LOOP_LABEL]]
|
||||
; CHECK-NEXT: b.ne [[LOOP_LABEL]]
|
||||
; CHECK-NEXT: [[IFEND_LABEL]]:
|
||||
; Epilogue code.
|
||||
; CHECK: add sp, sp, #16
|
||||
@ -409,9 +409,9 @@ declare void @llvm.va_end(i8*)
|
||||
;
|
||||
; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ; %for.body
|
||||
; Inline asm statement.
|
||||
; CHECK: sub [[IV]], [[IV]], #1
|
||||
; CHECK: subs [[IV]], [[IV]], #1
|
||||
; CHECK: add x19, x19, #1
|
||||
; CHECK: cbnz [[IV]], [[LOOP_LABEL]]
|
||||
; CHECK: b.ne [[LOOP_LABEL]]
|
||||
; Next BB.
|
||||
; CHECK: mov w0, wzr
|
||||
; Epilogue code.
|
||||
|
||||
169
test/CodeGen/AArch64/cond-br-tuning.ll
Normal file
169
test/CodeGen/AArch64/cond-br-tuning.ll
Normal file
@ -0,0 +1,169 @@
|
||||
; RUN: llc < %s -O3 -mtriple=aarch64-eabi -verify-machineinstrs | FileCheck %s
|
||||
|
||||
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
|
||||
target triple = "aarch64-linaro-linux-gnueabi"
|
||||
|
||||
; CMN is an alias of ADDS.
|
||||
; CHECK-LABEL: test_add_cbz:
|
||||
; CHECK: cmn w0, w1
|
||||
; CHECK: b.eq
|
||||
; CHECK: ret
|
||||
define void @test_add_cbz(i32 %a, i32 %b, i32* %ptr) {
|
||||
%c = add nsw i32 %a, %b
|
||||
%d = icmp ne i32 %c, 0
|
||||
br i1 %d, label %L1, label %L2
|
||||
L1:
|
||||
store i32 0, i32* %ptr, align 4
|
||||
ret void
|
||||
L2:
|
||||
store i32 1, i32* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_add_cbz_multiple_use:
|
||||
; CHECK: adds
|
||||
; CHECK: b.eq
|
||||
; CHECK: ret
|
||||
define void @test_add_cbz_multiple_use(i32 %a, i32 %b, i32* %ptr) {
|
||||
%c = add nsw i32 %a, %b
|
||||
%d = icmp ne i32 %c, 0
|
||||
br i1 %d, label %L1, label %L2
|
||||
L1:
|
||||
store i32 0, i32* %ptr, align 4
|
||||
ret void
|
||||
L2:
|
||||
store i32 %c, i32* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_add_cbz_64:
|
||||
; CHECK: cmn x0, x1
|
||||
; CHECK: b.eq
|
||||
define void @test_add_cbz_64(i64 %a, i64 %b, i64* %ptr) {
|
||||
%c = add nsw i64 %a, %b
|
||||
%d = icmp ne i64 %c, 0
|
||||
br i1 %d, label %L1, label %L2
|
||||
L1:
|
||||
store i64 0, i64* %ptr, align 4
|
||||
ret void
|
||||
L2:
|
||||
store i64 1, i64* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_and_cbz:
|
||||
; CHECK: tst w0, #0x6
|
||||
; CHECK: b.eq
|
||||
define void @test_and_cbz(i32 %a, i32* %ptr) {
|
||||
%c = and i32 %a, 6
|
||||
%d = icmp ne i32 %c, 0
|
||||
br i1 %d, label %L1, label %L2
|
||||
L1:
|
||||
store i32 0, i32* %ptr, align 4
|
||||
ret void
|
||||
L2:
|
||||
store i32 1, i32* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_bic_cbnz:
|
||||
; CHECK: bics wzr, w1, w0
|
||||
; CHECK: b.ne
|
||||
define void @test_bic_cbnz(i32 %a, i32 %b, i32* %ptr) {
|
||||
%c = and i32 %a, %b
|
||||
%d = icmp eq i32 %c, %b
|
||||
br i1 %d, label %L1, label %L2
|
||||
L1:
|
||||
store i32 0, i32* %ptr, align 4
|
||||
ret void
|
||||
L2:
|
||||
store i32 1, i32* %ptr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_add_tbz:
|
||||
; CHECK: adds
|
||||
; CHECK: b.ge
|
||||
; CHECK: ret
|
||||
define void @test_add_tbz(i32 %a, i32 %b, i32* %ptr) {
|
||||
entry:
|
||||
%add = add nsw i32 %a, %b
|
||||
%cmp36 = icmp sge i32 %add, 0
|
||||
br i1 %cmp36, label %L2, label %L1
|
||||
L1:
|
||||
store i32 %add, i32* %ptr, align 8
|
||||
br label %L2
|
||||
L2:
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_subs_tbz:
|
||||
; CHECK: subs
|
||||
; CHECK: b.ge
|
||||
; CHECK: ret
|
||||
define void @test_subs_tbz(i32 %a, i32 %b, i32* %ptr) {
|
||||
entry:
|
||||
%sub = sub nsw i32 %a, %b
|
||||
%cmp36 = icmp sge i32 %sub, 0
|
||||
br i1 %cmp36, label %L2, label %L1
|
||||
L1:
|
||||
store i32 %sub, i32* %ptr, align 8
|
||||
br label %L2
|
||||
L2:
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_add_tbnz
|
||||
; CHECK: adds
|
||||
; CHECK: b.lt
|
||||
; CHECK: ret
|
||||
define void @test_add_tbnz(i32 %a, i32 %b, i32* %ptr) {
|
||||
entry:
|
||||
%add = add nsw i32 %a, %b
|
||||
%cmp36 = icmp slt i32 %add, 0
|
||||
br i1 %cmp36, label %L2, label %L1
|
||||
L1:
|
||||
store i32 %add, i32* %ptr, align 8
|
||||
br label %L2
|
||||
L2:
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_subs_tbnz
|
||||
; CHECK: subs
|
||||
; CHECK: b.lt
|
||||
; CHECK: ret
|
||||
define void @test_subs_tbnz(i32 %a, i32 %b, i32* %ptr) {
|
||||
entry:
|
||||
%sub = sub nsw i32 %a, %b
|
||||
%cmp36 = icmp slt i32 %sub, 0
|
||||
br i1 %cmp36, label %L2, label %L1
|
||||
L1:
|
||||
store i32 %sub, i32* %ptr, align 8
|
||||
br label %L2
|
||||
L2:
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @foo()
|
||||
declare void @bar(i32)
|
||||
|
||||
; Don't transform since the call will clobber the NZCV bits.
|
||||
; CHECK-LABEL: test_call_clobber:
|
||||
; CHECK: and w[[DST:[0-9]+]], w1, #0x6
|
||||
; CHECK: bl bar
|
||||
; CHECK: cbnz w[[DST]]
|
||||
define void @test_call_clobber(i32 %unused, i32 %a) {
|
||||
entry:
|
||||
%c = and i32 %a, 6
|
||||
call void @bar(i32 %c)
|
||||
%tobool = icmp eq i32 %c, 0
|
||||
br i1 %tobool, label %if.end, label %if.then
|
||||
|
||||
if.then:
|
||||
tail call void @foo()
|
||||
unreachable
|
||||
|
||||
if.end:
|
||||
ret void
|
||||
}
|
||||
@ -7,8 +7,8 @@ declare void @foobar(i32 %v0, i32 %v1)
|
||||
|
||||
; Make sure sub is scheduled in front of cbnz
|
||||
; CHECK-LABEL: test_sub_cbz:
|
||||
; CHECK: sub w[[SUBRES:[0-9]+]], w0, #13
|
||||
; CHECK-NEXT: cbnz w[[SUBRES]], {{.?LBB[0-9_]+}}
|
||||
; CHECK: subs w[[SUBRES:[0-9]+]], w0, #13
|
||||
; CHECK: b.ne {{.?LBB[0-9_]+}}
|
||||
define void @test_sub_cbz(i32 %a0, i32 %a1) {
|
||||
entry:
|
||||
; except for the fusion opportunity the sub/add should be equal so the
|
||||
|
||||
@ -13,8 +13,8 @@
|
||||
; CHECK: ldur [[R3:x[0-9]+]], {{\[}}x29, [[SLOT0]]{{\]}}
|
||||
; CHECK: ldr [[GUARD_ADDR:x[0-9]+]], {{\[}}[[GUARD_PAGE]], ___stack_chk_guard@GOTPAGEOFF{{\]}}
|
||||
; CHECK: ldr [[GUARD:x[0-9]+]], {{\[}}[[GUARD_ADDR]]{{\]}}
|
||||
; CHECK: sub [[R4:x[0-9]+]], [[GUARD]], [[R3]]
|
||||
; CHECK: cbnz [[R4]], LBB
|
||||
; CHECK: cmp [[GUARD]], [[R3]]
|
||||
; CHECK: b.ne LBB
|
||||
|
||||
define i32 @test_stack_guard_remat2() {
|
||||
entry:
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -O1 -mtriple=aarch64-eabi | FileCheck %s
|
||||
; RUN: llc < %s -O1 -mtriple=aarch64-eabi -aarch64-enable-cond-br-tune=false | FileCheck %s
|
||||
|
||||
declare void @t()
|
||||
|
||||
|
||||
@ -13,8 +13,8 @@
|
||||
; CHECK: .LBB0_2:
|
||||
; CHECK: ldr w0, [x[[REG2]]]
|
||||
; CHECK: bl bar
|
||||
; CHECK: sub w[[REG3:[0-9]+]], w{{[0-9]+}}, #1
|
||||
; CHECK: cbnz w[[REG3]], .LBB0_2
|
||||
; CHECK: subs w[[REG3:[0-9]+]], w{{[0-9]+}}, #1
|
||||
; CHECK: b.ne .LBB0_2
|
||||
|
||||
define void @test1(i32 %n) local_unnamed_addr {
|
||||
entry:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user