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MIPS DSP: add vector load/store patterns.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164744 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-09-27 01:50:59 +00:00
parent 44aebe85e3
commit 7509ec18d1
3 changed files with 45 additions and 0 deletions
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13
lib/Target/Mips/MipsDSPInstrInfo.td
View File

@ -18,3 +18,16 @@ def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
// Patterns.
class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
Pat<pattern, result>, Requires<[pred]>;
def : DSPPat<(v2i16 (load addr:$a)),
(v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
def : DSPPat<(v4i8 (load addr:$a)),
(v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
def : DSPPat<(store (v2i16 DSPRegs:$val), addr:$a),
(SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
def : DSPPat<(store (v4i8 DSPRegs:$val), addr:$a),
(SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;

5
lib/Target/Mips/MipsInstrInfo.td
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@ -1233,3 +1233,8 @@ include "MipsCondMov.td"
include "Mips16InstrFormats.td"
include "Mips16InstrInfo.td"
// DSP
include "MipsDSPInstrFormats.td"
include "MipsDSPInstrInfo.td"

27
test/CodeGen/Mips/vector-load-store.ll Normal file
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@ -0,0 +1,27 @@
; RUN: llc -march=mipsel -mattr=+dsp < %s | FileCheck %s
@g1 = common global <2 x i16> zeroinitializer, align 4
@g0 = common global <2 x i16> zeroinitializer, align 4
@g3 = common global <4 x i8> zeroinitializer, align 4
@g2 = common global <4 x i8> zeroinitializer, align 4
define void @func_v2i16() nounwind {
entry:
; CHECK: lw
; CHECK: sw
%0 = load <2 x i16>* @g1, align 4
store <2 x i16> %0, <2 x i16>* @g0, align 4
ret void
}
define void @func_v4i8() nounwind {
entry:
; CHECK: lw
; CHECK: sw
%0 = load <4 x i8>* @g3, align 4
store <4 x i8> %0, <4 x i8>* @g2, align 4
ret void
}