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[mips][microMIPS] Implement SWM and LWM aliases
Differential Revision: http://reviews.llvm.org/D5820 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227373 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -182,6 +182,10 @@ class MipsAsmParser : public MCTargetAsmParser {
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void expandMemInst(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions, bool isLoad,
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bool isImmOpnd);
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bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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bool reportParseError(Twine ErrorMsg);
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bool reportParseError(SMLoc Loc, Twine ErrorMsg);
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@ -1532,6 +1536,8 @@ bool MipsAsmParser::needsExpansion(MCInst &Inst) {
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case Mips::LoadAddr32Reg:
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case Mips::LoadImm64Reg:
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case Mips::B_MM_Pseudo:
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case Mips::LWM_MM:
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case Mips::SWM_MM:
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return true;
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default:
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return false;
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@ -1556,6 +1562,9 @@ bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
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return expandLoadAddressReg(Inst, IDLoc, Instructions);
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case Mips::B_MM_Pseudo:
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return expandUncondBranchMMPseudo(Inst, IDLoc, Instructions);
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case Mips::SWM_MM:
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case Mips::LWM_MM:
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return expandLoadStoreMultiple(Inst, IDLoc, Instructions);
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}
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}
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@ -2000,6 +2009,29 @@ void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
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TempInst.clear();
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}
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bool
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MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions) {
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unsigned OpNum = Inst.getNumOperands();
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unsigned Opcode = Inst.getOpcode();
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unsigned NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM32_MM : Mips::LWM32_MM;
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assert (Inst.getOperand(OpNum - 1).isImm() &&
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Inst.getOperand(OpNum - 2).isReg() &&
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Inst.getOperand(OpNum - 3).isReg() && "Invalid instruction operand.");
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if (OpNum < 8 && Inst.getOperand(OpNum - 1).getImm() <= 60 &&
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Inst.getOperand(OpNum - 1).getImm() >= 0 &&
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Inst.getOperand(OpNum - 2).getReg() == Mips::SP &&
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Inst.getOperand(OpNum - 3).getReg() == Mips::RA)
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// It can be implemented as SWM16 or LWM16 instruction.
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NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MM : Mips::LWM16_MM;
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Inst.setOpcode(NewOpcode);
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Instructions.push_back(Inst);
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return false;
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}
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unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
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// As described by the Mips32r2 spec, the registers Rd and Rs for
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// jalr.hb must be different.
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@ -697,6 +697,19 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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def SWP_MM : StorePairMM<"swp">, LWM_FM_MM<0x9>;
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def LWP_MM : LoadPairMM<"lwp">, LWM_FM_MM<0x1>;
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/// Load and Store multiple pseudo Instructions
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class LoadWordMultMM<string instr_asm > :
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MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),
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!strconcat(instr_asm, "\t$rt, $addr")> ;
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class StoreWordMultMM<string instr_asm > :
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MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
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!strconcat(instr_asm, "\t$rt, $addr")> ;
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def SWM_MM : StoreWordMultMM<"swm">;
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def LWM_MM : LoadWordMultMM<"lwm">;
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/// Move Conditional
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def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
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NoItinerary>, ADD_FM_MM<0, 0x58>;
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@ -34,6 +34,14 @@
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# CHECK-EL: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x84,0x20,0x08,0xd0]
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# CHECK-EL: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x12,0x45]
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# CHECK-EL: swm16 $16, $17, $ra, 8($sp) # encoding: [0x52,0x45]
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# CHECK-EL: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x12,0x45]
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# CHECK-EL: lwm32 $16, $17, $ra, 64($sp) # encoding: [0x5d,0x22,0x40,0x50]
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# CHECK-EL: lwm32 $16, $17, $ra, 8($4) # encoding: [0x44,0x22,0x08,0x50]
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# CHECK-EL: lwm32 $16, $17, 8($sp) # encoding: [0x5d,0x20,0x08,0x50]
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# CHECK-EL: swm16 $16, $17, $ra, 8($sp) # encoding: [0x52,0x45]
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# CHECK-EL: swm32 $16, $17, $ra, 64($sp) # encoding: [0x5d,0x22,0x40,0xd0]
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# CHECK-EL: swm32 $16, $17, $ra, 8($4) # encoding: [0x44,0x22,0x08,0xd0]
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# CHECK-EL: swm32 $16, $17, 8($sp) # encoding: [0x5d,0x20,0x08,0xd0]
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# CHECK-EL: swp $16, 8($4) # encoding: [0x04,0x22,0x08,0x90]
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# CHECK-EL: lwp $16, 8($4) # encoding: [0x04,0x22,0x08,0x10]
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#------------------------------------------------------------------------------
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@ -64,6 +72,14 @@
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# CHECK-EB: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0xd0,0x08]
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# CHECK-EB: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x12]
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# CHECK-EB: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x52]
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# CHECK-EB: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x12]
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# CHECK-EB: lwm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0x50,0x40]
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# CHECK-EB: lwm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0x50,0x08]
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# CHECK-EB: lwm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0x50,0x08]
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# CHECK-EB: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x52]
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# CHECK-EB: swm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0xd0,0x40]
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# CHECK-EB: swm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0xd0,0x08]
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# CHECK-EB: swm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0xd0,0x08]
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# CHECK-EB: swp $16, 8($4) # encoding: [0x22,0x04,0x90,0x08]
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# CHECK-EB: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08]
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lb $5, 8($4)
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@ -91,5 +107,13 @@
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swm32 $16 - $19, 8($4)
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lwm16 $16, $17, $ra, 8($sp)
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swm16 $16, $17, $ra, 8($sp)
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lwm $16, $17, $ra, 8($sp)
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lwm $16, $17, $ra, 64($sp)
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lwm $16, $17, $ra, 8($4)
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lwm $16, $17, 8($sp)
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swm $16, $17, $ra, 8($sp)
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swm $16, $17, $ra, 64($sp)
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swm $16, $17, $ra, 8($4)
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swm $16, $17, 8($sp)
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swp $16, 8($4)
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lwp $16, 8($4)
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