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https://github.com/RPCSX/llvm.git
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First step towards V9 instructions in the V8 backend, two conditional move
patterns. This allows emission of this code:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
move %icc, %i0, %i2
or %g0, %i2, %i0
restore %g0, %g0, %g0
retl
nop
instead of this:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
be .LBBt1_2 !
nop
.LBBt1_1: !
or %g0, %i2, %i0
.LBBt1_2: !
restore %g0, %g0, %g0
retl
nop
for this:
int %t1(int %a, int %b, int %c) {
%tmp.2 = seteq int %a, %b
%tmp3 = select bool %tmp.2, int %a, int %c
ret int %tmp3
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25809 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
6f63001214
commit
76afdc9a80
@ -1,10 +1,4 @@
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Meta TODO list:
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1. Create a new DAG -> DAG instruction selector, by adding patterns to the
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instructions.
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2. ???
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3. profit!
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To-do
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-----
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@ -12,4 +6,5 @@ To-do
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address all of the time.
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* We can fold small constant offsets into the %hi/%lo references to constant
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pool addresses as well.
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* When in V9 mode, register allocate %icc[0-3].
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@ -850,9 +850,15 @@ SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
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namespace {
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class SparcV8DAGToDAGISel : public SelectionDAGISel {
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SparcV8TargetLowering V8Lowering;
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/// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const SparcV8Subtarget &Subtarget;
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public:
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SparcV8DAGToDAGISel(TargetMachine &TM)
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: SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
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: SelectionDAGISel(V8Lowering), V8Lowering(TM),
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Subtarget(TM.getSubtarget<SparcV8Subtarget>()) {
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}
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SDOperand Select(SDOperand Op);
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@ -17,6 +17,23 @@
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include "SparcV8InstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Feature predicates.
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//===----------------------------------------------------------------------===//
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// HasV9 - This predicate is true when the target processor supports V9
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// instructions. Note that the machine may be running in 32-bit mode.
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def HasV9 : Predicate<"Subtarget.isV9()">;
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// HasVIS - This is true when the target processor has VIS extensions.
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def HasVIS : Predicate<"Subtarget.isVIS()">;
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// UseDeprecatedInsts - This predicate is true when the target processor is a
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// V8, or when it is V9 but the V8 deprecated instructions are efficient enough
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// to use when appropriate. In either of these cases, the instruction selector
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// will pick deprecated instructions.
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def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
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//===----------------------------------------------------------------------===//
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// Instruction Pattern Stuff
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//===----------------------------------------------------------------------===//
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@ -168,6 +185,7 @@ let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
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imm:$Cond, FCC))]>;
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}
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// Section A.3 - Synthetic Instructions, p. 85
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// special cases of JMPL:
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let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in {
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@ -706,6 +724,24 @@ def FCMPD : F3_3<2, 0b110101, 0b001010010,
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"fcmpd $src1, $src2\n\tnop",
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[(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>;
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//===----------------------------------------------------------------------===//
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// V9 Instructions
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//===----------------------------------------------------------------------===//
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// V9 Conditional Moves.
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let Predicates = [HasV9], isTwoAddress = 1 in {
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// FIXME: Add instruction encodings for the JIT some day.
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def MOVNE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movne %icc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selecticc IntRegs:$F, IntRegs:$T, 22, ICC))]>;
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def MOVEQ : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"move %icc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selecticc IntRegs:$F, IntRegs:$T, 17, ICC))]>;
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}
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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//===----------------------------------------------------------------------===//
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@ -1,10 +1,4 @@
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Meta TODO list:
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1. Create a new DAG -> DAG instruction selector, by adding patterns to the
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instructions.
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2. ???
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3. profit!
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To-do
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-----
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@ -12,4 +6,5 @@ To-do
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address all of the time.
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* We can fold small constant offsets into the %hi/%lo references to constant
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pool addresses as well.
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* When in V9 mode, register allocate %icc[0-3].
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@ -850,9 +850,15 @@ SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
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namespace {
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class SparcV8DAGToDAGISel : public SelectionDAGISel {
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SparcV8TargetLowering V8Lowering;
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/// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const SparcV8Subtarget &Subtarget;
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public:
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SparcV8DAGToDAGISel(TargetMachine &TM)
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: SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
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: SelectionDAGISel(V8Lowering), V8Lowering(TM),
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Subtarget(TM.getSubtarget<SparcV8Subtarget>()) {
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}
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SDOperand Select(SDOperand Op);
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@ -17,6 +17,23 @@
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include "SparcV8InstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Feature predicates.
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//===----------------------------------------------------------------------===//
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// HasV9 - This predicate is true when the target processor supports V9
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// instructions. Note that the machine may be running in 32-bit mode.
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def HasV9 : Predicate<"Subtarget.isV9()">;
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// HasVIS - This is true when the target processor has VIS extensions.
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def HasVIS : Predicate<"Subtarget.isVIS()">;
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// UseDeprecatedInsts - This predicate is true when the target processor is a
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// V8, or when it is V9 but the V8 deprecated instructions are efficient enough
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// to use when appropriate. In either of these cases, the instruction selector
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// will pick deprecated instructions.
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def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
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//===----------------------------------------------------------------------===//
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// Instruction Pattern Stuff
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//===----------------------------------------------------------------------===//
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@ -168,6 +185,7 @@ let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
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imm:$Cond, FCC))]>;
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}
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// Section A.3 - Synthetic Instructions, p. 85
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// special cases of JMPL:
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let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in {
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@ -706,6 +724,24 @@ def FCMPD : F3_3<2, 0b110101, 0b001010010,
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"fcmpd $src1, $src2\n\tnop",
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[(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>;
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//===----------------------------------------------------------------------===//
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// V9 Instructions
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//===----------------------------------------------------------------------===//
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// V9 Conditional Moves.
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let Predicates = [HasV9], isTwoAddress = 1 in {
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// FIXME: Add instruction encodings for the JIT some day.
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def MOVNE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"movne %icc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selecticc IntRegs:$F, IntRegs:$T, 22, ICC))]>;
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def MOVEQ : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
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"move %icc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selecticc IntRegs:$F, IntRegs:$T, 17, ICC))]>;
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}
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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//===----------------------------------------------------------------------===//
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