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CodeGen: Add a hook for getFenceOperandTy

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Currently the operand type for ATOMIC_FENCE assumes value type of a pointer in address space 0.
This is fine for most targets. However for amdgcn target, the size of pointer in address space 0
depends on triple environment. For amdgiz environment, it is 64 bit but for other environment it is
32 bit. On the other hand, amdgcn target expects 32 bit fence operands independent of the target
triple environment. Therefore a hook is need in target lowering for getting the fence operand type.

This patch has no effect on targets other than amdgcn.

Differential Revision: https://reviews.llvm.org/D32186


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301215 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Yaxun Liu 2017-04-24 18:26:27 +00:00
parent 724559be8d
commit 76c532ddba
5 changed files with 33 additions and 2 deletions
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6
include/llvm/Target/TargetLowering.h
View File

@ -236,6 +236,12 @@ public:
return getPointerTy(DL, DL.getAllocaAddrSpace());
}
/// Return the type for operands of fence.
/// TODO: Let fence operands be of i32 type and remove this.
virtual MVT getFenceOperandTy(const DataLayout &DL) const {
return getPointerTy(DL);
}
/// EVT is not used in-tree, but is used by out-of-tree target.
/// A documentation for this function would be nice...
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;

4
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -3969,9 +3969,9 @@ void SelectionDAGBuilder::visitFence(const FenceInst &I) {
SDValue Ops[3];
Ops[0] = getRoot();
Ops[1] = DAG.getConstant((unsigned)I.getOrdering(), dl,
TLI.getPointerTy(DAG.getDataLayout()));
TLI.getFenceOperandTy(DAG.getDataLayout()));
Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
TLI.getPointerTy(DAG.getDataLayout()));
TLI.getFenceOperandTy(DAG.getDataLayout()));
DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
}

4
lib/Target/AMDGPU/AMDGPUISelLowering.h
View File

@ -231,6 +231,10 @@ public:
AMDGPUAS getAMDGPUAS() const {
return AMDGPUASI;
}
MVT getFenceOperandTy(const DataLayout &DL) const override {
return MVT::i32;
}
};
namespace AMDGPUISD {

6
lib/Target/AMDGPU/SIInstructions.td
View File

@ -94,6 +94,12 @@ defm V_INTERP_MOV_F32 : VINTRP_m <
//===----------------------------------------------------------------------===//
// Pseudo Instructions
//===----------------------------------------------------------------------===//
def ATOMIC_FENCE : SPseudoInstSI<
(outs), (ins i32imm:$ordering, i32imm:$scope),
[(atomic_fence (i32 imm:$ordering), (i32 imm:$scope))],
"ATOMIC_FENCE $ordering, $scope"> {
let hasSideEffects = 1;
}
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in {

15
test/CodeGen/AMDGPU/fence-amdgiz.ll Normal file
View File

@ -0,0 +1,15 @@
; RUN: llc < %s | FileCheck %s
target datalayout = "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"
target triple = "amdgcn-amd-amdhsa-amdgizcl"
; CHECK_LABEL: atomic_fence
; CHECK: BB#0:
; CHECK: ATOMIC_FENCE 4, 1
; CHECK: s_endpgm
define amdgpu_kernel void @atomic_fence() {
fence acquire
ret void
}