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[Powerpc darwin] AsmParser Base implementation.
This is a base implementation of the powerpc-apple-darwin asm parser dialect.
* Enables infrastructure (essentially isDarwin()) and fixes up the parsing of asm directives to separate out ELF and MachO/Darwin additions.
* Enables parsing of {r,f,v}XX as register identifiers.
* Enables parsing of lo16() hi16() and ha16() as modifiers.
The changes to the test case are from David Fang (fangism).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197324 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Iain Sandoe
parent
da48260ed4
commit
771005ce98
@ -177,6 +177,7 @@ class PPCAsmParser : public MCTargetAsmParser {
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MCAsmParser &Parser;
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const MCInstrInfo &MII;
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bool IsPPC64;
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bool IsDarwin;
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MCAsmParser &getParser() const { return Parser; }
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MCAsmLexer &getLexer() const { return Parser.getLexer(); }
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@ -185,6 +186,7 @@ class PPCAsmParser : public MCTargetAsmParser {
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bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
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bool isPPC64() const { return IsPPC64; }
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bool isDarwin() const { return IsDarwin; }
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bool MatchRegisterName(const AsmToken &Tok,
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unsigned &RegNo, int64_t &IntVal);
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@ -195,12 +197,14 @@ class PPCAsmParser : public MCTargetAsmParser {
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PPCMCExpr::VariantKind &Variant);
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const MCExpr *FixupVariantKind(const MCExpr *E);
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bool ParseExpression(const MCExpr *&EVal);
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bool ParseDarwinExpression(const MCExpr *&EVal);
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bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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bool ParseDirectiveWord(unsigned Size, SMLoc L);
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bool ParseDirectiveTC(unsigned Size, SMLoc L);
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bool ParseDirectiveMachine(SMLoc L);
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bool ParseDarwinDirectiveMachine(SMLoc L);
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bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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@ -227,6 +231,7 @@ public:
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Triple TheTriple(STI.getTargetTriple());
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IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
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TheTriple.getArch() == Triple::ppc64le);
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IsDarwin = TheTriple.isMacOSX();
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// Initialize the set of available features.
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setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
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}
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@ -1081,10 +1086,16 @@ FixupVariantKind(const MCExpr *E) {
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llvm_unreachable("Invalid expression kind!");
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}
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/// Parse an expression. This differs from the default "parseExpression"
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/// in that it handles complex \code @l/@ha \endcode modifiers.
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/// ParseExpression. This differs from the default "parseExpression" in that
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/// it handles modifiers.
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bool PPCAsmParser::
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ParseExpression(const MCExpr *&EVal) {
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if (isDarwin())
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return ParseDarwinExpression(EVal);
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// (ELF Platforms)
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// Handle \code @l/@ha \endcode
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if (getParser().parseExpression(EVal))
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return true;
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@ -1098,6 +1109,55 @@ ParseExpression(const MCExpr *&EVal) {
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return false;
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}
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/// ParseDarwinExpression. (MachO Platforms)
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/// This differs from the default "parseExpression" in that it handles detection
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/// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present,
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/// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
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/// syntax form so it is done here. TODO: Determine if there is merit in arranging
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/// for this to be done at a higher level.
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bool PPCAsmParser::
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ParseDarwinExpression(const MCExpr *&EVal) {
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PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
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switch (getLexer().getKind()) {
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default:
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break;
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case AsmToken::Identifier:
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// Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
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// something starting with any other char should be part of the
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// asm syntax. If handwritten asm includes an identifier like lo16,
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// then all bets are off - but no-one would do that, right?
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StringRef poss = Parser.getTok().getString();
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if (poss.equals_lower("lo16")) {
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Variant = PPCMCExpr::VK_PPC_LO;
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} else if (poss.equals_lower("hi16")) {
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Variant = PPCMCExpr::VK_PPC_HI;
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} else if (poss.equals_lower("ha16")) {
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Variant = PPCMCExpr::VK_PPC_HA;
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}
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if (Variant != PPCMCExpr::VK_PPC_None) {
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Parser.Lex(); // Eat the xx16
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if (getLexer().isNot(AsmToken::LParen))
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return Error(Parser.getTok().getLoc(), "expected '('");
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Parser.Lex(); // Eat the '('
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}
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break;
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}
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if (getParser().parseExpression(EVal))
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return true;
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if (Variant != PPCMCExpr::VK_PPC_None) {
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if (getLexer().isNot(AsmToken::RParen))
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return Error(Parser.getTok().getLoc(), "expected ')'");
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Parser.Lex(); // Eat the ')'
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EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext());
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}
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return false;
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}
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/// ParseOperand
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/// This handles registers in the form 'NN', '%rNN' for ELF platforms and
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/// rNN for MachO.
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bool PPCAsmParser::
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ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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SMLoc S = Parser.getTok().getLoc();
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@ -1121,12 +1181,27 @@ ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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}
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return Error(S, "invalid register name");
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case AsmToken::Identifier:
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// Note that non-register-name identifiers from the compiler will begin
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// with '_', 'L'/'l' or '"'. Of course, handwritten asm could include
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// identifiers like r31foo - so we fall through in the event that parsing
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// a register name fails.
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if (isDarwin()) {
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unsigned RegNo;
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int64_t IntVal;
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if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
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Parser.Lex(); // Eat the identifier token.
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Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
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Operands.push_back(Op);
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return false;
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}
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}
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// Fall-through to process non-register-name identifiers as expression.
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// All other expressions
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case AsmToken::LParen:
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case AsmToken::Plus:
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case AsmToken::Minus:
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case AsmToken::Integer:
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case AsmToken::Identifier:
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case AsmToken::Dot:
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case AsmToken::Dollar:
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if (!ParseExpression(EVal))
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@ -1177,11 +1252,25 @@ ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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break;
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case AsmToken::Integer:
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if (getParser().parseAbsoluteExpression(IntVal) ||
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if (!isDarwin()) {
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if (getParser().parseAbsoluteExpression(IntVal) ||
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IntVal < 0 || IntVal > 31)
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return Error(S, "invalid register number");
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} else {
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return Error(S, "unexpected integer value");
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}
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break;
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case AsmToken::Identifier:
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if (isDarwin()) {
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unsigned RegNo;
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if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
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Parser.Lex(); // Eat the identifier token.
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break;
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}
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}
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// Fall-through..
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default:
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return Error(S, "invalid memory operand");
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}
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@ -1261,14 +1350,19 @@ ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
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/// ParseDirective parses the PPC specific directives
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bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
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StringRef IDVal = DirectiveID.getIdentifier();
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if (IDVal == ".word")
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return ParseDirectiveWord(2, DirectiveID.getLoc());
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if (IDVal == ".llong")
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return ParseDirectiveWord(8, DirectiveID.getLoc());
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if (IDVal == ".tc")
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return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
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if (IDVal == ".machine")
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return ParseDirectiveMachine(DirectiveID.getLoc());
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if (!isDarwin()) {
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if (IDVal == ".word")
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return ParseDirectiveWord(2, DirectiveID.getLoc());
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if (IDVal == ".llong")
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return ParseDirectiveWord(8, DirectiveID.getLoc());
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if (IDVal == ".tc")
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return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
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if (IDVal == ".machine")
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return ParseDirectiveMachine(DirectiveID.getLoc());
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} else {
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if (IDVal == ".machine")
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return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
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}
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return true;
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}
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@ -1314,7 +1408,7 @@ bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
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return ParseDirectiveWord(Size, L);
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}
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/// ParseDirectiveMachine
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/// ParseDirectiveMachine (ELF platforms)
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/// ::= .machine [ cpu | "push" | "pop" ]
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bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
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if (getLexer().isNot(AsmToken::Identifier) &&
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@ -1338,6 +1432,33 @@ bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
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return false;
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}
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/// ParseDarwinDirectiveMachine (Mach-o platforms)
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/// ::= .machine cpu-identifier
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bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
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if (getLexer().isNot(AsmToken::Identifier) &&
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getLexer().isNot(AsmToken::String))
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return Error(L, "unexpected token in directive");
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StringRef CPU = Parser.getTok().getIdentifier();
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Parser.Lex();
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// FIXME: this is only the 'default' set of cpu variants.
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// However we don't act on this information at present, this is simply
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// allowing parsing to proceed with minimal sanity checking.
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if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64")
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return Error(L, "unrecognized cpu type");
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if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc"))
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return Error(L, "wrong cpu type specified for 64bit");
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if (!isPPC64() && CPU == "ppc64")
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return Error(L, "wrong cpu type specified for 32bit");
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if (getLexer().isNot(AsmToken::EndOfStatement))
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return Error(L, "unexpected token in directive");
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return false;
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}
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/// Force static initialization.
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extern "C" void LLVMInitializePowerPCAsmParser() {
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RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
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@ -1,14 +1,10 @@
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; This tests for the basic implementation of PPCMachObjectWriter.cpp,
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; which is responsible for writing mach-o relocation entries for (PIC)
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; PowerPC objects.
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; NOTE: Darwin PPC asm syntax is not yet supported by PPCAsmParser,
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; so this test case uses ELF PPC asm syntax to produce a mach-o object.
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; Once PPCAsmParser supports darwin asm syntax, this test case should
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; be updated accordingly.
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; RUN: llvm-mc -filetype=obj -relocation-model=pic -mcpu=g4 -triple=powerpc-apple-darwin8 %s -o - | llvm-readobj -relocations | FileCheck -check-prefix=DARWIN-G4-DUMP %s
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; .machine ppc7400
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.machine ppc7400
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.section __TEXT,__textcoal_nt,coalesced,pure_instructions
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.section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32
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.section __TEXT,__text,regular,pure_instructions
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@ -16,40 +12,40 @@
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.align 4
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_main: ; @main
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; BB#0: ; %entry
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mflr 0
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stw 31, -4(1)
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stw 0, 8(1)
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stwu 1, -80(1)
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mflr r0
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stw r31, -4(r1)
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stw r0, 8(r1)
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stwu r1, -80(r1)
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bl L0$pb
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L0$pb:
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mr 31, 1
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li 5, 0
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mr r31, r1
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li r5, 0
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mflr 2
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stw 3, 68(31)
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stw 5, 72(31)
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stw 4, 64(31)
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addis 2, 2, (L_.str-L0$pb)@ha
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la 3, (L_.str-L0$pb)@l(2)
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stw r3, 68(r31)
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stw r5, 72(r31)
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stw r4, 64(r31)
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addis r2, r2, ha16(L_.str-L0$pb)
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la r3, lo16(L_.str-L0$pb)(r2)
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bl L_puts$stub
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li 3, 0
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addi 1, 1, 80
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lwz 0, 8(1)
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lwz 31, -4(1)
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mtlr 0
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li r3, 0
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addi r1, r1, 80
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lwz r0, 8(r1)
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lwz r31, -4(r1)
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mtlr r0
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blr
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.section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32
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.align 4
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L_puts$stub:
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.indirect_symbol _puts
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mflr 0
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mflr r0
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bcl 20, 31, L_puts$stub$tmp
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L_puts$stub$tmp:
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mflr 11
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addis 11, 11, (L_puts$lazy_ptr-L_puts$stub$tmp)@ha
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mtlr 0
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lwzu 12, (L_puts$lazy_ptr-L_puts$stub$tmp)@l(11)
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mtctr 12
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mflr r11
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addis r11, r11, ha16(L_puts$lazy_ptr-L_puts$stub$tmp)
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mtlr r0
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lwzu r12, lo16(L_puts$lazy_ptr-L_puts$stub$tmp)(r11)
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mtctr r12
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bctr
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.section __DATA,__la_symbol_ptr,lazy_symbol_pointers
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L_puts$lazy_ptr:
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