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R600: Optimize another selectcc case

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fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
     selectcc x, y, a, b, cc

Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176700 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2013-03-08 15:37:11 +00:00
parent 1454cb86be
commit 7893d29c62
2 changed files with 49 additions and 13 deletions
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31
lib/Target/R600/R600ISelLowering.cpp
View File

@ -1042,6 +1042,9 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
case ISD::SELECT_CC: {
// fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
// selectcc x, y, a, b, inv(cc)
//
// fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
// selectcc x, y, a, b, cc
SDValue LHS = N->getOperand(0);
if (LHS.getOpcode() != ISD::SELECT_CC) {
return SDValue();
@ -1050,24 +1053,30 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
SDValue RHS = N->getOperand(1);
SDValue True = N->getOperand(2);
SDValue False = N->getOperand(3);
ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
if (LHS.getOperand(2).getNode() != True.getNode() ||
LHS.getOperand(3).getNode() != False.getNode() ||
RHS.getNode() != False.getNode() ||
cast<CondCodeSDNode>(N->getOperand(4))->get() != ISD::SETEQ) {
RHS.getNode() != False.getNode()) {
return SDValue();
}
ISD::CondCode CCOpcode = cast<CondCodeSDNode>(LHS->getOperand(4))->get();
CCOpcode = ISD::getSetCCInverse(
CCOpcode, LHS.getOperand(0).getValueType().isInteger());
return DAG.getSelectCC(N->getDebugLoc(),
LHS.getOperand(0),
LHS.getOperand(1),
LHS.getOperand(2),
LHS.getOperand(3),
CCOpcode);
switch (NCC) {
default: return SDValue();
case ISD::SETNE: return LHS;
case ISD::SETEQ: {
ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
LHSCC = ISD::getSetCCInverse(LHSCC,
LHS.getOperand(0).getValueType().isInteger());
return DAG.getSelectCC(N->getDebugLoc(),
LHS.getOperand(0),
LHS.getOperand(1),
LHS.getOperand(2),
LHS.getOperand(3),
LHSCC);
}
}
}
case AMDGPUISD::EXPORT: {
SDValue Arg = N->getOperand(1);
if (Arg.getOpcode() != ISD::BUILD_VECTOR)

31
test/CodeGen/R600/selectcc-opt.ll
View File

@ -25,10 +25,37 @@ ENDIF:
ret void
}
; Test a CND*_INT instruction with float true/false values
; Same as test_a, but the branch labels are swapped to produce the inverse cc
; for the icmp instruction
; CHECK: @test_b
; CHECK: SET{{[GTEQN]+}}_DX10
; CHECK-NEXT: PRED_
define void @test_b(i32 addrspace(1)* %out, float %in) {
entry:
%0 = fcmp ult float %in, 0.0
%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
%2 = fsub float -0.000000e+00, %1
%3 = fptosi float %2 to i32
%4 = bitcast i32 %3 to float
%5 = bitcast float %4 to i32
%6 = icmp ne i32 %5, 0
br i1 %6, label %ENDIF, label %IF
IF:
%7 = getelementptr i32 addrspace(1)* %out, i32 1
store i32 0, i32 addrspace(1)* %7
br label %ENDIF
ENDIF:
store i32 0, i32 addrspace(1)* %out
ret void
}
; Test a CND*_INT instruction with float true/false values
; CHECK: @test_c
; CHECK: CND{{[GTE]+}}_INT
define void @test_b(float addrspace(1)* %out, i32 %in) {
define void @test_c(float addrspace(1)* %out, i32 %in) {
entry:
%0 = icmp sgt i32 %in, 0
%1 = select i1 %0, float 2.0, float 3.0