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PR7458: Try commuting Thumb2 instruction operands to put them into 2-address

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form so they can be narrowed to 16-bit instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106762 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-06-24 16:50:20 +00:00
parent f0e1b89421
commit 789fef987f
3 changed files with 20 additions and 5 deletions
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14
lib/Target/ARM/Thumb2SizeReduction.cpp
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@ -451,11 +451,18 @@ Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
if (ReduceLimit2Addr != -1 && ((int)Num2Addrs >= ReduceLimit2Addr))
return false;
const TargetInstrDesc &TID = MI->getDesc();
unsigned Reg0 = MI->getOperand(0).getReg();
unsigned Reg1 = MI->getOperand(1).getReg();
if (Reg0 != Reg1)
return false;
if (Reg0 != Reg1) {
// Try to commute the operands to make it a 2-address instruction.
unsigned CommOpIdx1, CommOpIdx2;
if (!TII->findCommutedOpIndices(MI, CommOpIdx1, CommOpIdx2) ||
CommOpIdx1 != 1 || MI->getOperand(CommOpIdx2).getReg() != Reg0)
return false;
MachineInstr *CommutedMI = TII->commuteInstruction(MI);
if (!CommutedMI)
return false;
}
if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
return false;
if (Entry.Imm2Limit) {
@ -484,6 +491,7 @@ Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
bool HasCC = false;
bool CCDead = false;
const TargetInstrDesc &TID = MI->getDesc();
if (TID.hasOptionalDef()) {
unsigned NumOps = TID.getNumOperands();
HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);

9
test/CodeGen/Thumb2/thumb2-eor.ll
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@ -9,11 +9,18 @@ define i32 @f1(i32 %a, i32 %b) {
define i32 @f2(i32 %a, i32 %b) {
; CHECK: f2:
; CHECK: eor.w r0, r1, r0
; CHECK: eors r0, r1
%tmp = xor i32 %b, %a
ret i32 %tmp
}
define i32 @f2b(i32 %a, i32 %b, i32 %c) {
; CHECK: f2b:
; CHECK: eor.w r0, r1, r2
%tmp = xor i32 %b, %c
ret i32 %tmp
}
define i32 @f3(i32 %a, i32 %b) {
; CHECK: f3:
; CHECK: eor.w r0, r0, r1, lsl #5

2
test/CodeGen/Thumb2/thumb2-uxtb.ll
View File

@ -87,7 +87,7 @@ define i32 @test10(i32 %p0) {
; CHECK: and.w r0, r1, r0, lsr #7
; CHECK: lsrs r1, r0, #5
; CHECK: uxtb16 r1, r1
; CHECK: orr.w r0, r1, r0
; CHECK: orrs r0, r1
%tmp1 = lshr i32 %p0, 7 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16253176 ; <i32> [#uses=2]