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AVX-512: Added intrinsics for VCVT* instructions.
All SKX forms. All VCVT instructions for float/double/int/long types. Differential Revision: http://reviews.llvm.org/D11343 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242877 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
5015f9766b
commit
78d824a9ff
@ -3753,51 +3753,480 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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// Vector convert
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_avx512_mask_cvttps2dq_512: GCCBuiltin<"__builtin_ia32_cvttps2dq512_mask">,
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Intrinsic<[llvm_v16i32_ty], [llvm_v16f32_ty, llvm_v16i32_ty,
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llvm_i16_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_cvttps2udq_512: GCCBuiltin<"__builtin_ia32_cvttps2udq512_mask">,
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Intrinsic<[llvm_v16i32_ty], [llvm_v16f32_ty, llvm_v16i32_ty,
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llvm_i16_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_cvttpd2dq_512: GCCBuiltin<"__builtin_ia32_cvttpd2dq512_mask">,
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Intrinsic<[llvm_v8i32_ty], [llvm_v8f64_ty, llvm_v8i32_ty,
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llvm_i8_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_cvttpd2udq_512: GCCBuiltin<"__builtin_ia32_cvttpd2udq512_mask">,
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Intrinsic<[llvm_v8i32_ty], [llvm_v8f64_ty, llvm_v8i32_ty,
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llvm_i8_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_avx512_mask_cvtdq2pd_128 :
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GCCBuiltin<"__builtin_ia32_cvtdq2pd128_mask">,
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Intrinsic<[llvm_v2f64_ty],
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[llvm_v4i32_ty, llvm_v2f64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtdq2pd_256 :
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GCCBuiltin<"__builtin_ia32_cvtdq2pd256_mask">,
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Intrinsic<[llvm_v4f64_ty],
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[llvm_v4i32_ty, llvm_v4f64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtdq2pd_512 :
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GCCBuiltin<"__builtin_ia32_cvtdq2pd512_mask">,
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Intrinsic<[llvm_v8f64_ty],
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[llvm_v8i32_ty, llvm_v8f64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtdq2ps_128 :
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GCCBuiltin<"__builtin_ia32_cvtdq2ps128_mask">,
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Intrinsic<[llvm_v4f32_ty],
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[llvm_v4i32_ty, llvm_v4f32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtdq2ps_256 :
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GCCBuiltin<"__builtin_ia32_cvtdq2ps256_mask">,
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Intrinsic<[llvm_v8f32_ty],
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[llvm_v8i32_ty, llvm_v8f32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtdq2ps_512 :
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GCCBuiltin<"__builtin_ia32_cvtdq2ps512_mask">,
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Intrinsic<[llvm_v16f32_ty],
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[llvm_v16i32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtpd2dq_128 :
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GCCBuiltin<"__builtin_ia32_cvtpd2dq128_mask">,
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v2f64_ty, llvm_v4i32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtpd2dq_256 :
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GCCBuiltin<"__builtin_ia32_cvtpd2dq256_mask">,
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v4f64_ty, llvm_v4i32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtpd2dq_512 :
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GCCBuiltin<"__builtin_ia32_cvtpd2dq512_mask">,
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Intrinsic<[llvm_v8i32_ty],
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[llvm_v8f64_ty, llvm_v8i32_ty, llvm_i8_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtpd2ps_256 :
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GCCBuiltin<"__builtin_ia32_cvtpd2ps256_mask">,
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Intrinsic<[llvm_v4f32_ty],
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[llvm_v4f64_ty, llvm_v4f32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtpd2ps_512 :
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GCCBuiltin<"__builtin_ia32_cvtpd2ps512_mask">,
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Intrinsic<[llvm_v8f32_ty],
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[llvm_v8f64_ty, llvm_v8f32_ty, llvm_i8_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtpd2ps :
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GCCBuiltin<"__builtin_ia32_cvtpd2ps_mask">,
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Intrinsic<[llvm_v4f32_ty],
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[llvm_v2f64_ty, llvm_v4f32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtpd2qq_128 :
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GCCBuiltin<"__builtin_ia32_cvtpd2qq128_mask">,
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Intrinsic<[llvm_v2i64_ty],
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[llvm_v2f64_ty, llvm_v2i64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtpd2qq_256 :
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GCCBuiltin<"__builtin_ia32_cvtpd2qq256_mask">,
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Intrinsic<[llvm_v4i64_ty],
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[llvm_v4f64_ty, llvm_v4i64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtpd2qq_512 :
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GCCBuiltin<"__builtin_ia32_cvtpd2qq512_mask">,
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Intrinsic<[llvm_v8i64_ty],
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[llvm_v8f64_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtpd2udq_128 :
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GCCBuiltin<"__builtin_ia32_cvtpd2udq128_mask">,
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v2f64_ty, llvm_v4i32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtpd2udq_256 :
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GCCBuiltin<"__builtin_ia32_cvtpd2udq256_mask">,
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v4f64_ty, llvm_v4i32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtpd2udq_512 :
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GCCBuiltin<"__builtin_ia32_cvtpd2udq512_mask">,
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Intrinsic<[llvm_v8i32_ty],
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[llvm_v8f64_ty, llvm_v8i32_ty, llvm_i8_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtpd2uqq_128 :
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GCCBuiltin<"__builtin_ia32_cvtpd2uqq128_mask">,
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Intrinsic<[llvm_v2i64_ty],
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[llvm_v2f64_ty, llvm_v2i64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtpd2uqq_256 :
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GCCBuiltin<"__builtin_ia32_cvtpd2uqq256_mask">,
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Intrinsic<[llvm_v4i64_ty],
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[llvm_v4f64_ty, llvm_v4i64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtpd2uqq_512 :
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GCCBuiltin<"__builtin_ia32_cvtpd2uqq512_mask">,
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Intrinsic<[llvm_v8i64_ty],
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[llvm_v8f64_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtps2dq_128 :
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GCCBuiltin<"__builtin_ia32_cvtps2dq128_mask">,
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v4f32_ty, llvm_v4i32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtps2dq_256 :
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GCCBuiltin<"__builtin_ia32_cvtps2dq256_mask">,
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Intrinsic<[llvm_v8i32_ty],
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[llvm_v8f32_ty, llvm_v8i32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtps2dq_512 :
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GCCBuiltin<"__builtin_ia32_cvtps2dq512_mask">,
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Intrinsic<[llvm_v16i32_ty],
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[llvm_v16f32_ty, llvm_v16i32_ty, llvm_i16_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtps2pd_128 :
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GCCBuiltin<"__builtin_ia32_cvtps2pd128_mask">,
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Intrinsic<[llvm_v2f64_ty],
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[llvm_v4f32_ty, llvm_v2f64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtps2pd_256 :
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GCCBuiltin<"__builtin_ia32_cvtps2pd256_mask">,
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Intrinsic<[llvm_v4f64_ty],
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[llvm_v4f32_ty, llvm_v4f64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtps2pd_512 :
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GCCBuiltin<"__builtin_ia32_cvtps2pd512_mask">,
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Intrinsic<[llvm_v8f64_ty],
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[llvm_v8f32_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtps2qq_128 :
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GCCBuiltin<"__builtin_ia32_cvtps2qq128_mask">,
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Intrinsic<[llvm_v2i64_ty],
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[llvm_v4f32_ty, llvm_v2i64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtps2qq_256 :
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GCCBuiltin<"__builtin_ia32_cvtps2qq256_mask">,
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Intrinsic<[llvm_v4i64_ty],
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[llvm_v4f32_ty, llvm_v4i64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtps2qq_512 :
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GCCBuiltin<"__builtin_ia32_cvtps2qq512_mask">,
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Intrinsic<[llvm_v8i64_ty],
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[llvm_v8f32_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtps2udq_128 :
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GCCBuiltin<"__builtin_ia32_cvtps2udq128_mask">,
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v4f32_ty, llvm_v4i32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtps2udq_256 :
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GCCBuiltin<"__builtin_ia32_cvtps2udq256_mask">,
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Intrinsic<[llvm_v8i32_ty],
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[llvm_v8f32_ty, llvm_v8i32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtps2udq_512 :
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GCCBuiltin<"__builtin_ia32_cvtps2udq512_mask">,
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Intrinsic<[llvm_v16i32_ty],
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[llvm_v16f32_ty, llvm_v16i32_ty, llvm_i16_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtps2uqq_128 :
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GCCBuiltin<"__builtin_ia32_cvtps2uqq128_mask">,
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Intrinsic<[llvm_v2i64_ty],
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[llvm_v4f32_ty, llvm_v2i64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtps2uqq_256 :
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GCCBuiltin<"__builtin_ia32_cvtps2uqq256_mask">,
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Intrinsic<[llvm_v4i64_ty],
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[llvm_v4f32_ty, llvm_v4i64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtps2uqq_512 :
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GCCBuiltin<"__builtin_ia32_cvtps2uqq512_mask">,
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Intrinsic<[llvm_v8i64_ty],
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[llvm_v8f32_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtqq2pd_128 :
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GCCBuiltin<"__builtin_ia32_cvtqq2pd128_mask">,
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Intrinsic<[llvm_v2f64_ty],
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[llvm_v2i64_ty, llvm_v2f64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtqq2pd_256 :
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GCCBuiltin<"__builtin_ia32_cvtqq2pd256_mask">,
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Intrinsic<[llvm_v4f64_ty],
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[llvm_v4i64_ty, llvm_v4f64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtqq2pd_512 :
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GCCBuiltin<"__builtin_ia32_cvtqq2pd512_mask">,
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Intrinsic<[llvm_v8f64_ty],
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[llvm_v8i64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtqq2ps_128 :
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GCCBuiltin<"__builtin_ia32_cvtqq2ps128_mask">,
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Intrinsic<[llvm_v4f32_ty],
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[llvm_v2i64_ty, llvm_v4f32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtqq2ps_256 :
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GCCBuiltin<"__builtin_ia32_cvtqq2ps256_mask">,
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Intrinsic<[llvm_v4f32_ty],
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[llvm_v4i64_ty, llvm_v4f32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvtqq2ps_512 :
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GCCBuiltin<"__builtin_ia32_cvtqq2ps512_mask">,
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Intrinsic<[llvm_v8f32_ty],
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[llvm_v8i64_ty, llvm_v8f32_ty, llvm_i8_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvttpd2dq_128 :
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GCCBuiltin<"__builtin_ia32_cvttpd2dq128_mask">,
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v2f64_ty, llvm_v4i32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvttpd2dq_256 :
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GCCBuiltin<"__builtin_ia32_cvttpd2dq256_mask">,
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v4f64_ty, llvm_v4i32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvttpd2dq_512 :
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GCCBuiltin<"__builtin_ia32_cvttpd2dq512_mask">,
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Intrinsic<[llvm_v8i32_ty],
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[llvm_v8f64_ty, llvm_v8i32_ty, llvm_i8_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvttpd2qq_128 :
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GCCBuiltin<"__builtin_ia32_cvttpd2qq128_mask">,
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Intrinsic<[llvm_v2i64_ty],
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[llvm_v2f64_ty, llvm_v2i64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvttpd2qq_256 :
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GCCBuiltin<"__builtin_ia32_cvttpd2qq256_mask">,
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Intrinsic<[llvm_v4i64_ty],
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[llvm_v4f64_ty, llvm_v4i64_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvttpd2qq_512 :
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GCCBuiltin<"__builtin_ia32_cvttpd2qq512_mask">,
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Intrinsic<[llvm_v8i64_ty],
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[llvm_v8f64_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvttpd2udq_128 :
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GCCBuiltin<"__builtin_ia32_cvttpd2udq128_mask">,
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v2f64_ty, llvm_v4i32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvttpd2udq_256 :
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GCCBuiltin<"__builtin_ia32_cvttpd2udq256_mask">,
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v4f64_ty, llvm_v4i32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvttpd2udq_512 :
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GCCBuiltin<"__builtin_ia32_cvttpd2udq512_mask">,
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Intrinsic<[llvm_v8i32_ty],
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[llvm_v8f64_ty, llvm_v8i32_ty, llvm_i8_ty, llvm_i32_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_cvttpd2uqq_128 :
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GCCBuiltin<"__builtin_ia32_cvttpd2uqq128_mask">,
|
||||
Intrinsic<[llvm_v2i64_ty],
|
||||
[llvm_v2f64_ty, llvm_v2i64_ty, llvm_i8_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvttpd2uqq_256 :
|
||||
GCCBuiltin<"__builtin_ia32_cvttpd2uqq256_mask">,
|
||||
Intrinsic<[llvm_v4i64_ty],
|
||||
[llvm_v4f64_ty, llvm_v4i64_ty, llvm_i8_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvttpd2uqq_512 :
|
||||
GCCBuiltin<"__builtin_ia32_cvttpd2uqq512_mask">,
|
||||
Intrinsic<[llvm_v8i64_ty],
|
||||
[llvm_v8f64_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvttps2dq_128 :
|
||||
GCCBuiltin<"__builtin_ia32_cvttps2dq128_mask">,
|
||||
Intrinsic<[llvm_v4i32_ty],
|
||||
[llvm_v4f32_ty, llvm_v4i32_ty, llvm_i8_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvttps2dq_256 :
|
||||
GCCBuiltin<"__builtin_ia32_cvttps2dq256_mask">,
|
||||
Intrinsic<[llvm_v8i32_ty],
|
||||
[llvm_v8f32_ty, llvm_v8i32_ty, llvm_i8_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvttps2dq_512 :
|
||||
GCCBuiltin<"__builtin_ia32_cvttps2dq512_mask">,
|
||||
Intrinsic<[llvm_v16i32_ty],
|
||||
[llvm_v16f32_ty, llvm_v16i32_ty, llvm_i16_ty, llvm_i32_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvttps2qq_128 :
|
||||
GCCBuiltin<"__builtin_ia32_cvttps2qq128_mask">,
|
||||
Intrinsic<[llvm_v2i64_ty],
|
||||
[llvm_v4f32_ty, llvm_v2i64_ty, llvm_i8_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvttps2qq_256 :
|
||||
GCCBuiltin<"__builtin_ia32_cvttps2qq256_mask">,
|
||||
Intrinsic<[llvm_v4i64_ty],
|
||||
[llvm_v4f32_ty, llvm_v4i64_ty, llvm_i8_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvttps2qq_512 :
|
||||
GCCBuiltin<"__builtin_ia32_cvttps2qq512_mask">,
|
||||
Intrinsic<[llvm_v8i64_ty],
|
||||
[llvm_v8f32_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvttps2udq_128 :
|
||||
GCCBuiltin<"__builtin_ia32_cvttps2udq128_mask">,
|
||||
Intrinsic<[llvm_v4i32_ty],
|
||||
[llvm_v4f32_ty, llvm_v4i32_ty, llvm_i8_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvttps2udq_256 :
|
||||
GCCBuiltin<"__builtin_ia32_cvttps2udq256_mask">,
|
||||
Intrinsic<[llvm_v8i32_ty],
|
||||
[llvm_v8f32_ty, llvm_v8i32_ty, llvm_i8_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvttps2udq_512 :
|
||||
GCCBuiltin<"__builtin_ia32_cvttps2udq512_mask">,
|
||||
Intrinsic<[llvm_v16i32_ty],
|
||||
[llvm_v16f32_ty, llvm_v16i32_ty, llvm_i16_ty, llvm_i32_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvttps2uqq_128 :
|
||||
GCCBuiltin<"__builtin_ia32_cvttps2uqq128_mask">,
|
||||
Intrinsic<[llvm_v2i64_ty],
|
||||
[llvm_v4f32_ty, llvm_v2i64_ty, llvm_i8_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvttps2uqq_256 :
|
||||
GCCBuiltin<"__builtin_ia32_cvttps2uqq256_mask">,
|
||||
Intrinsic<[llvm_v4i64_ty],
|
||||
[llvm_v4f32_ty, llvm_v4i64_ty, llvm_i8_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvttps2uqq_512 :
|
||||
GCCBuiltin<"__builtin_ia32_cvttps2uqq512_mask">,
|
||||
Intrinsic<[llvm_v8i64_ty],
|
||||
[llvm_v8f32_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvtudq2pd_128 :
|
||||
GCCBuiltin<"__builtin_ia32_cvtudq2pd128_mask">,
|
||||
Intrinsic<[llvm_v2f64_ty],
|
||||
[llvm_v4i32_ty, llvm_v2f64_ty, llvm_i8_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvtudq2pd_256 :
|
||||
GCCBuiltin<"__builtin_ia32_cvtudq2pd256_mask">,
|
||||
Intrinsic<[llvm_v4f64_ty],
|
||||
[llvm_v4i32_ty, llvm_v4f64_ty, llvm_i8_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvtudq2pd_512 :
|
||||
GCCBuiltin<"__builtin_ia32_cvtudq2pd512_mask">,
|
||||
Intrinsic<[llvm_v8f64_ty],
|
||||
[llvm_v8i32_ty, llvm_v8f64_ty, llvm_i8_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvtudq2ps_128 :
|
||||
GCCBuiltin<"__builtin_ia32_cvtudq2ps128_mask">,
|
||||
Intrinsic<[llvm_v4f32_ty],
|
||||
[llvm_v4i32_ty, llvm_v4f32_ty, llvm_i8_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvtudq2ps_256 :
|
||||
GCCBuiltin<"__builtin_ia32_cvtudq2ps256_mask">,
|
||||
Intrinsic<[llvm_v8f32_ty],
|
||||
[llvm_v8i32_ty, llvm_v8f32_ty, llvm_i8_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvtudq2ps_512 :
|
||||
GCCBuiltin<"__builtin_ia32_cvtudq2ps512_mask">,
|
||||
Intrinsic<[llvm_v16f32_ty],
|
||||
[llvm_v16i32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvtuqq2pd_128 :
|
||||
GCCBuiltin<"__builtin_ia32_cvtuqq2pd128_mask">,
|
||||
Intrinsic<[llvm_v2f64_ty],
|
||||
[llvm_v2i64_ty, llvm_v2f64_ty, llvm_i8_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvtuqq2pd_256 :
|
||||
GCCBuiltin<"__builtin_ia32_cvtuqq2pd256_mask">,
|
||||
Intrinsic<[llvm_v4f64_ty],
|
||||
[llvm_v4i64_ty, llvm_v4f64_ty, llvm_i8_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvtuqq2pd_512 :
|
||||
GCCBuiltin<"__builtin_ia32_cvtuqq2pd512_mask">,
|
||||
Intrinsic<[llvm_v8f64_ty],
|
||||
[llvm_v8i64_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvtuqq2ps_128 :
|
||||
GCCBuiltin<"__builtin_ia32_cvtuqq2ps128_mask">,
|
||||
Intrinsic<[llvm_v4f32_ty],
|
||||
[llvm_v2i64_ty, llvm_v4f32_ty, llvm_i8_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvtuqq2ps_256 :
|
||||
GCCBuiltin<"__builtin_ia32_cvtuqq2ps256_mask">,
|
||||
Intrinsic<[llvm_v4f32_ty],
|
||||
[llvm_v4i64_ty, llvm_v4f32_ty, llvm_i8_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_cvtuqq2ps_512 :
|
||||
GCCBuiltin<"__builtin_ia32_cvtuqq2ps512_mask">,
|
||||
Intrinsic<[llvm_v8f32_ty],
|
||||
[llvm_v8i64_ty, llvm_v8f32_ty, llvm_i8_ty, llvm_i32_ty],
|
||||
[IntrNoMem]>;
|
||||
|
||||
def int_x86_avx512_mask_rndscale_ps_512: GCCBuiltin<"__builtin_ia32_rndscaleps_mask">,
|
||||
Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty, llvm_i32_ty, llvm_v16f32_ty,
|
||||
llvm_i16_ty, llvm_i32_ty], [IntrNoMem]>;
|
||||
def int_x86_avx512_mask_rndscale_pd_512: GCCBuiltin<"__builtin_ia32_rndscalepd_mask">,
|
||||
Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty, llvm_i32_ty, llvm_v8f64_ty,
|
||||
llvm_i8_ty, llvm_i32_ty], [IntrNoMem]>;
|
||||
def int_x86_avx512_mask_cvtps2dq_512: GCCBuiltin<"__builtin_ia32_cvtps2dq512_mask">,
|
||||
Intrinsic<[llvm_v16i32_ty], [llvm_v16f32_ty, llvm_v16i32_ty,
|
||||
llvm_i16_ty, llvm_i32_ty], [IntrNoMem]>;
|
||||
def int_x86_avx512_mask_cvtpd2dq_512: GCCBuiltin<"__builtin_ia32_cvtpd2dq512_mask">,
|
||||
Intrinsic<[llvm_v8i32_ty], [llvm_v8f64_ty, llvm_v8i32_ty,
|
||||
llvm_i8_ty, llvm_i32_ty], [IntrNoMem]>;
|
||||
def int_x86_avx512_mask_cvtps2udq_512: GCCBuiltin<"__builtin_ia32_cvtps2udq512_mask">,
|
||||
Intrinsic<[llvm_v16i32_ty], [llvm_v16f32_ty, llvm_v16i32_ty,
|
||||
llvm_i16_ty, llvm_i32_ty], [IntrNoMem]>;
|
||||
def int_x86_avx512_mask_cvtpd2udq_512: GCCBuiltin<"__builtin_ia32_cvtpd2udq512_mask">,
|
||||
Intrinsic<[llvm_v8i32_ty], [llvm_v8f64_ty, llvm_v8i32_ty,
|
||||
llvm_i8_ty, llvm_i32_ty], [IntrNoMem]>;
|
||||
def int_x86_avx512_mask_cvtdq2ps_512 : GCCBuiltin<"__builtin_ia32_cvtdq2ps512_mask">,
|
||||
Intrinsic<[llvm_v16f32_ty], [llvm_v16i32_ty, llvm_v16f32_ty,
|
||||
llvm_i16_ty, llvm_i32_ty], [IntrNoMem]>;
|
||||
def int_x86_avx512_mask_cvtdq2pd_512 : GCCBuiltin<"__builtin_ia32_cvtdq2pd512_mask">,
|
||||
Intrinsic<[llvm_v8f64_ty], [llvm_v8i32_ty, llvm_v8f64_ty,
|
||||
llvm_i8_ty], [IntrNoMem]>;
|
||||
def int_x86_avx512_mask_cvtudq2ps_512 : GCCBuiltin<"__builtin_ia32_cvtudq2ps512_mask">,
|
||||
Intrinsic<[llvm_v16f32_ty], [llvm_v16i32_ty, llvm_v16f32_ty,
|
||||
llvm_i16_ty, llvm_i32_ty], [IntrNoMem]>;
|
||||
def int_x86_avx512_mask_cvtudq2pd_512 : GCCBuiltin<"__builtin_ia32_cvtudq2pd512_mask">,
|
||||
Intrinsic<[llvm_v8f64_ty], [llvm_v8i32_ty, llvm_v8f64_ty,
|
||||
llvm_i8_ty], [IntrNoMem]>;
|
||||
def int_x86_avx512_mask_cvtpd2ps_512 : GCCBuiltin<"__builtin_ia32_cvtpd2ps512_mask">,
|
||||
Intrinsic<[llvm_v8f32_ty], [llvm_v8f64_ty, llvm_v8f32_ty,
|
||||
llvm_i8_ty, llvm_i32_ty], [IntrNoMem]>;
|
||||
}
|
||||
|
||||
// Vector load with broadcast
|
||||
|
||||
@ -15358,28 +15358,45 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget
|
||||
SDValue PassThru = Op.getOperand(2);
|
||||
SDValue Mask = Op.getOperand(3);
|
||||
SDValue RoundingMode;
|
||||
// We allways add rounding mode to the Node.
|
||||
// If the rounding mode is not specified, we add the
|
||||
// "current direction" mode.
|
||||
if (Op.getNumOperands() == 4)
|
||||
RoundingMode = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
|
||||
RoundingMode =
|
||||
DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
|
||||
else
|
||||
RoundingMode = Op.getOperand(4);
|
||||
unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
|
||||
if (IntrWithRoundingModeOpcode != 0) {
|
||||
unsigned Round = cast<ConstantSDNode>(RoundingMode)->getZExtValue();
|
||||
if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION)
|
||||
if (IntrWithRoundingModeOpcode != 0)
|
||||
if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
|
||||
X86::STATIC_ROUNDING::CUR_DIRECTION)
|
||||
return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
|
||||
dl, Op.getValueType(), Src, RoundingMode),
|
||||
Mask, PassThru, Subtarget, DAG);
|
||||
}
|
||||
return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
|
||||
RoundingMode),
|
||||
Mask, PassThru, Subtarget, DAG);
|
||||
}
|
||||
case INTR_TYPE_1OP_MASK: {
|
||||
SDValue Src = Op.getOperand(1);
|
||||
SDValue Passthru = Op.getOperand(2);
|
||||
SDValue PassThru = Op.getOperand(2);
|
||||
SDValue Mask = Op.getOperand(3);
|
||||
// We add rounding mode to the Node when
|
||||
// - RM Opcode is specified and
|
||||
// - RM is not "current direction".
|
||||
unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
|
||||
if (IntrWithRoundingModeOpcode != 0) {
|
||||
SDValue Rnd = Op.getOperand(4);
|
||||
unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
|
||||
if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
|
||||
return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
|
||||
dl, Op.getValueType(),
|
||||
Src, Rnd),
|
||||
Mask, PassThru, Subtarget, DAG);
|
||||
}
|
||||
}
|
||||
return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
|
||||
Mask, Passthru, Subtarget, DAG);
|
||||
Mask, PassThru, Subtarget, DAG);
|
||||
}
|
||||
case INTR_TYPE_SCALAR_MASK_RM: {
|
||||
SDValue Src1 = Op.getOperand(1);
|
||||
|
||||
@ -416,6 +416,163 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
|
||||
X86_INTRINSIC_DATA(avx512_mask_compress_q_512, COMPRESS_EXPAND_IN_REG,
|
||||
X86ISD::COMPRESS, 0),
|
||||
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtdq2pd_128, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::CVTDQ2PD, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtdq2pd_256, INTR_TYPE_1OP_MASK,
|
||||
ISD::SINT_TO_FP, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtdq2pd_512, INTR_TYPE_1OP_MASK,
|
||||
ISD::SINT_TO_FP, 0), // no rm
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtdq2ps_128, INTR_TYPE_1OP_MASK,
|
||||
ISD::SINT_TO_FP, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtdq2ps_256, INTR_TYPE_1OP_MASK,
|
||||
ISD::SINT_TO_FP, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtdq2ps_512, INTR_TYPE_1OP_MASK,
|
||||
ISD::SINT_TO_FP, ISD::SINT_TO_FP), //er
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtpd2dq_128, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_SINT_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtpd2dq_256, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_SINT_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtpd2dq_512, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_SINT_RND, X86ISD::FP_TO_SINT_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtpd2ps, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::VFPROUND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtpd2ps_256, INTR_TYPE_1OP_MASK_RM,
|
||||
ISD::FP_ROUND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtpd2ps_512, INTR_TYPE_1OP_MASK_RM,
|
||||
ISD::FP_ROUND, X86ISD::VFPROUND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtpd2qq_128, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_SINT_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtpd2qq_256, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_SINT_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtpd2qq_512, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_SINT_RND, X86ISD::FP_TO_SINT_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtpd2udq_128, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_UINT_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtpd2udq_256, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_UINT_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtpd2udq_512, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_UINT_RND, X86ISD::FP_TO_UINT_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtpd2uqq_128, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_UINT_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtpd2uqq_256, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_UINT_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtpd2uqq_512, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_UINT_RND, X86ISD::FP_TO_UINT_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtps2dq_128, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_SINT_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtps2dq_256, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_SINT_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtps2dq_512, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_SINT_RND, X86ISD::FP_TO_SINT_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtps2pd_128, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::VFPEXT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtps2pd_256, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_EXTEND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtps2pd_512, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_EXTEND, X86ISD::VFPEXT),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtps2qq_128, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_SINT_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtps2qq_256, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_SINT_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtps2qq_512, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_SINT_RND, X86ISD::FP_TO_SINT_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtps2udq_128, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_UINT_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtps2udq_256, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_UINT_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtps2udq_512, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_UINT_RND, X86ISD::FP_TO_UINT_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtps2uqq_128, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_UINT_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtps2uqq_256, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_UINT_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtps2uqq_512, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::FP_TO_UINT_RND, X86ISD::FP_TO_UINT_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtqq2pd_128, INTR_TYPE_1OP_MASK,
|
||||
ISD::SINT_TO_FP, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtqq2pd_256, INTR_TYPE_1OP_MASK,
|
||||
ISD::SINT_TO_FP, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtqq2pd_512, INTR_TYPE_1OP_MASK,
|
||||
ISD::SINT_TO_FP, ISD::SINT_TO_FP),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtqq2ps_128, INTR_TYPE_1OP_MASK,
|
||||
ISD::SINT_TO_FP, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtqq2ps_256, INTR_TYPE_1OP_MASK,
|
||||
ISD::SINT_TO_FP, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtqq2ps_512, INTR_TYPE_1OP_MASK,
|
||||
ISD::SINT_TO_FP, ISD::SINT_TO_FP),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttpd2dq_128, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_SINT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttpd2dq_256, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_SINT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttpd2dq_512, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_SINT, ISD::FP_TO_SINT),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttpd2qq_128, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_SINT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttpd2qq_256, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_SINT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttpd2qq_512, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_SINT, ISD::FP_TO_SINT),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttpd2udq_128, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_UINT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttpd2udq_256, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_UINT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttpd2udq_512, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_UINT, ISD::FP_TO_UINT),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttpd2uqq_128, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_UINT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttpd2uqq_256, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_UINT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttpd2uqq_512, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_UINT, ISD::FP_TO_UINT),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttps2dq_128, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_SINT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttps2dq_256, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_SINT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttps2dq_512, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_SINT, ISD::FP_TO_SINT),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttps2qq_128, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_SINT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttps2qq_256, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_SINT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttps2qq_512, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_SINT, ISD::FP_TO_SINT),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttps2udq_128, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_UINT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttps2udq_256, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_UINT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttps2udq_512, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_UINT, ISD::FP_TO_UINT),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttps2uqq_128, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_UINT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttps2uqq_256, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_UINT, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvttps2uqq_512, INTR_TYPE_1OP_MASK,
|
||||
ISD::FP_TO_UINT, ISD::FP_TO_UINT),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtudq2pd_128, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::CVTUDQ2PD, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtudq2pd_256, INTR_TYPE_1OP_MASK,
|
||||
ISD::UINT_TO_FP, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtudq2pd_512, INTR_TYPE_1OP_MASK,
|
||||
ISD::UINT_TO_FP, 0), // no rm
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtudq2ps_128, INTR_TYPE_1OP_MASK,
|
||||
ISD::UINT_TO_FP, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtudq2ps_256, INTR_TYPE_1OP_MASK,
|
||||
ISD::UINT_TO_FP, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtudq2ps_512, INTR_TYPE_1OP_MASK,
|
||||
ISD::UINT_TO_FP, ISD::UINT_TO_FP),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtuqq2pd_128, INTR_TYPE_1OP_MASK,
|
||||
ISD::UINT_TO_FP, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtuqq2pd_256, INTR_TYPE_1OP_MASK,
|
||||
ISD::UINT_TO_FP, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtuqq2pd_512, INTR_TYPE_1OP_MASK,
|
||||
ISD::UINT_TO_FP, ISD::UINT_TO_FP),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtuqq2ps_128, INTR_TYPE_1OP_MASK,
|
||||
ISD::UINT_TO_FP, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtuqq2ps_256, INTR_TYPE_1OP_MASK,
|
||||
ISD::UINT_TO_FP, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtuqq2ps_512, INTR_TYPE_1OP_MASK,
|
||||
ISD::UINT_TO_FP, ISD::UINT_TO_FP),
|
||||
|
||||
X86_INTRINSIC_DATA(avx512_mask_div_pd_128, INTR_TYPE_2OP_MASK, ISD::FDIV, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_div_pd_256, INTR_TYPE_2OP_MASK, ISD::FDIV, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_div_pd_512, INTR_TYPE_2OP_MASK, ISD::FDIV,
|
||||
|
||||
@ -3118,3 +3118,237 @@ define <16 x float>@test_int_x86_avx512_mask_scalef_ps_512(<16 x float> %x0, <16
|
||||
%res2 = fadd <16 x float> %res, %res1
|
||||
ret <16 x float> %res2
|
||||
}
|
||||
|
||||
declare <8 x double> @llvm.x86.avx512.mask.cvtdq2pd.512(<8 x i32>, <8 x double>, i8)
|
||||
|
||||
define <8 x double>@test_int_x86_avx512_mask_cvt_dq2pd_512(<8 x i32> %x0, <8 x double> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_dq2pd_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtdq2pd %ymm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtdq2pd %ymm0, %zmm0
|
||||
; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x double> @llvm.x86.avx512.mask.cvtdq2pd.512(<8 x i32> %x0, <8 x double> %x1, i8 %x2)
|
||||
%res1 = call <8 x double> @llvm.x86.avx512.mask.cvtdq2pd.512(<8 x i32> %x0, <8 x double> %x1, i8 -1)
|
||||
%res2 = fadd <8 x double> %res, %res1
|
||||
ret <8 x double> %res2
|
||||
}
|
||||
|
||||
declare <16 x float> @llvm.x86.avx512.mask.cvtdq2ps.512(<16 x i32>, <16 x float>, i16, i32)
|
||||
|
||||
define <16 x float>@test_int_x86_avx512_mask_cvt_dq2ps_512(<16 x i32> %x0, <16 x float> %x1, i16 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_dq2ps_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovw %edi, %k1
|
||||
; CHECK-NEXT: vcvtdq2ps %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtdq2ps {rn-sae}, %zmm0, %zmm0
|
||||
; CHECK-NEXT: vaddps %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <16 x float> @llvm.x86.avx512.mask.cvtdq2ps.512(<16 x i32> %x0, <16 x float> %x1, i16 %x2, i32 4)
|
||||
%res1 = call <16 x float> @llvm.x86.avx512.mask.cvtdq2ps.512(<16 x i32> %x0, <16 x float> %x1, i16 -1, i32 0)
|
||||
%res2 = fadd <16 x float> %res, %res1
|
||||
ret <16 x float> %res2
|
||||
}
|
||||
|
||||
declare <8 x i32> @llvm.x86.avx512.mask.cvtpd2dq.512(<8 x double>, <8 x i32>, i8, i32)
|
||||
|
||||
define <8 x i32>@test_int_x86_avx512_mask_cvt_pd2dq_512(<8 x double> %x0, <8 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2dq_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtpd2dq %zmm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvtpd2dq {rn-sae}, %zmm0, %ymm0
|
||||
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2dq.512(<8 x double> %x0, <8 x i32> %x1, i8 %x2, i32 4)
|
||||
%res1 = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2dq.512(<8 x double> %x0, <8 x i32> %x1, i8 -1, i32 0)
|
||||
%res2 = add <8 x i32> %res, %res1
|
||||
ret <8 x i32> %res2
|
||||
}
|
||||
|
||||
declare <8 x float> @llvm.x86.avx512.mask.cvtpd2ps.512(<8 x double>, <8 x float>, i8, i32)
|
||||
|
||||
define <8 x float>@test_int_x86_avx512_mask_cvt_pd2ps_512(<8 x double> %x0, <8 x float> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2ps_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtpd2ps %zmm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvtpd2ps {ru-sae}, %zmm0, %ymm0
|
||||
; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x float> @llvm.x86.avx512.mask.cvtpd2ps.512(<8 x double> %x0, <8 x float> %x1, i8 %x2, i32 4)
|
||||
%res1 = call <8 x float> @llvm.x86.avx512.mask.cvtpd2ps.512(<8 x double> %x0, <8 x float> %x1, i8 -1, i32 2)
|
||||
%res2 = fadd <8 x float> %res, %res1
|
||||
ret <8 x float> %res2
|
||||
}
|
||||
|
||||
declare <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double>, <8 x i32>, i8, i32)
|
||||
|
||||
define <8 x i32>@test_int_x86_avx512_mask_cvt_pd2udq_512(<8 x double> %x0, <8 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2udq_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtpd2udq {ru-sae}, %zmm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvtpd2udq {rn-sae}, %zmm0, %ymm0
|
||||
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double> %x0, <8 x i32> %x1, i8 %x2, i32 2)
|
||||
%res1 = call <8 x i32> @llvm.x86.avx512.mask.cvtpd2udq.512(<8 x double> %x0, <8 x i32> %x1, i8 -1, i32 0)
|
||||
%res2 = add <8 x i32> %res, %res1
|
||||
ret <8 x i32> %res2
|
||||
}
|
||||
|
||||
declare <16 x i32> @llvm.x86.avx512.mask.cvtps2dq.512(<16 x float>, <16 x i32>, i16, i32)
|
||||
|
||||
define <16 x i32>@test_int_x86_avx512_mask_cvt_ps2dq_512(<16 x float> %x0, <16 x i32> %x1, i16 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2dq_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovw %edi, %k1
|
||||
; CHECK-NEXT: vcvtps2dq {ru-sae}, %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtps2dq {rn-sae}, %zmm0, %zmm0
|
||||
; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <16 x i32> @llvm.x86.avx512.mask.cvtps2dq.512(<16 x float> %x0, <16 x i32> %x1, i16 %x2, i32 2)
|
||||
%res1 = call <16 x i32> @llvm.x86.avx512.mask.cvtps2dq.512(<16 x float> %x0, <16 x i32> %x1, i16 -1, i32 0)
|
||||
%res2 = add <16 x i32> %res, %res1
|
||||
ret <16 x i32> %res2
|
||||
}
|
||||
|
||||
declare <8 x double> @llvm.x86.avx512.mask.cvtps2pd.512(<8 x float>, <8 x double>, i8, i32)
|
||||
|
||||
define <8 x double>@test_int_x86_avx512_mask_cvt_ps2pd_512(<8 x float> %x0, <8 x double> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2pd_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtps2pd %ymm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtps2pd {sae}, %ymm0, %zmm0
|
||||
; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x double> @llvm.x86.avx512.mask.cvtps2pd.512(<8 x float> %x0, <8 x double> %x1, i8 %x2, i32 4)
|
||||
%res1 = call <8 x double> @llvm.x86.avx512.mask.cvtps2pd.512(<8 x float> %x0, <8 x double> %x1, i8 -1, i32 8)
|
||||
%res2 = fadd <8 x double> %res, %res1
|
||||
ret <8 x double> %res2
|
||||
}
|
||||
|
||||
declare <16 x i32> @llvm.x86.avx512.mask.cvtps2udq.512(<16 x float>, <16 x i32>, i16, i32)
|
||||
|
||||
define <16 x i32>@test_int_x86_avx512_mask_cvt_ps2udq_512(<16 x float> %x0, <16 x i32> %x1, i16 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2udq_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovw %edi, %k1
|
||||
; CHECK-NEXT: vcvtps2udq {ru-sae}, %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtps2udq {rn-sae}, %zmm0, %zmm0
|
||||
; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <16 x i32> @llvm.x86.avx512.mask.cvtps2udq.512(<16 x float> %x0, <16 x i32> %x1, i16 %x2, i32 2)
|
||||
%res1 = call <16 x i32> @llvm.x86.avx512.mask.cvtps2udq.512(<16 x float> %x0, <16 x i32> %x1, i16 -1, i32 0)
|
||||
%res2 = add <16 x i32> %res, %res1
|
||||
ret <16 x i32> %res2
|
||||
}
|
||||
|
||||
declare <8 x i32> @llvm.x86.avx512.mask.cvttpd2dq.512(<8 x double>, <8 x i32>, i8, i32)
|
||||
|
||||
define <8 x i32>@test_int_x86_avx512_mask_cvtt_pd2dq_512(<8 x double> %x0, <8 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2dq_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvttpd2dq %zmm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvttpd2dq {sae}, %zmm0, %ymm0
|
||||
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x i32> @llvm.x86.avx512.mask.cvttpd2dq.512(<8 x double> %x0, <8 x i32> %x1, i8 %x2, i32 4)
|
||||
%res1 = call <8 x i32> @llvm.x86.avx512.mask.cvttpd2dq.512(<8 x double> %x0, <8 x i32> %x1, i8 -1, i32 8)
|
||||
%res2 = add <8 x i32> %res, %res1
|
||||
ret <8 x i32> %res2
|
||||
}
|
||||
|
||||
declare <8 x double> @llvm.x86.avx512.mask.cvtudq2pd.512(<8 x i32>, <8 x double>, i8)
|
||||
|
||||
define <8 x double>@test_int_x86_avx512_mask_cvt_udq2pd_512(<8 x i32> %x0, <8 x double> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_udq2pd_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtudq2pd %ymm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtudq2pd %ymm0, %zmm0
|
||||
; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x double> @llvm.x86.avx512.mask.cvtudq2pd.512(<8 x i32> %x0, <8 x double> %x1, i8 %x2)
|
||||
%res1 = call <8 x double> @llvm.x86.avx512.mask.cvtudq2pd.512(<8 x i32> %x0, <8 x double> %x1, i8 -1)
|
||||
%res2 = fadd <8 x double> %res, %res1
|
||||
ret <8 x double> %res2
|
||||
}
|
||||
|
||||
|
||||
declare <16 x float> @llvm.x86.avx512.mask.cvtudq2ps.512(<16 x i32>, <16 x float>, i16, i32)
|
||||
|
||||
define <16 x float>@test_int_x86_avx512_mask_cvt_udq2ps_512(<16 x i32> %x0, <16 x float> %x1, i16 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_udq2ps_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovw %edi, %k1
|
||||
; CHECK-NEXT: vcvtudq2ps %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtudq2ps {rn-sae}, %zmm0, %zmm0
|
||||
; CHECK-NEXT: vaddps %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <16 x float> @llvm.x86.avx512.mask.cvtudq2ps.512(<16 x i32> %x0, <16 x float> %x1, i16 %x2, i32 4)
|
||||
%res1 = call <16 x float> @llvm.x86.avx512.mask.cvtudq2ps.512(<16 x i32> %x0, <16 x float> %x1, i16 -1, i32 0)
|
||||
%res2 = fadd <16 x float> %res, %res1
|
||||
ret <16 x float> %res2
|
||||
}
|
||||
|
||||
declare <8 x i32> @llvm.x86.avx512.mask.cvttpd2udq.512(<8 x double>, <8 x i32>, i8, i32)
|
||||
|
||||
define <8 x i32>@test_int_x86_avx512_mask_cvtt_pd2udq_512(<8 x double> %x0, <8 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2udq_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvttpd2udq %zmm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvttpd2udq {sae}, %zmm0, %ymm0
|
||||
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x i32> @llvm.x86.avx512.mask.cvttpd2udq.512(<8 x double> %x0, <8 x i32> %x1, i8 %x2, i32 4)
|
||||
%res1 = call <8 x i32> @llvm.x86.avx512.mask.cvttpd2udq.512(<8 x double> %x0, <8 x i32> %x1, i8 -1, i32 8)
|
||||
%res2 = add <8 x i32> %res, %res1
|
||||
ret <8 x i32> %res2
|
||||
}
|
||||
|
||||
declare <16 x i32> @llvm.x86.avx512.mask.cvttps2dq.512(<16 x float>, <16 x i32>, i16, i32)
|
||||
|
||||
define <16 x i32>@test_int_x86_avx512_mask_cvtt_ps2dq_512(<16 x float> %x0, <16 x i32> %x1, i16 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2dq_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovw %edi, %k1
|
||||
; CHECK-NEXT: vcvttps2dq %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vcvttps2dq {sae}, %zmm0, %zmm0
|
||||
; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <16 x i32> @llvm.x86.avx512.mask.cvttps2dq.512(<16 x float> %x0, <16 x i32> %x1, i16 %x2, i32 4)
|
||||
%res1 = call <16 x i32> @llvm.x86.avx512.mask.cvttps2dq.512(<16 x float> %x0, <16 x i32> %x1, i16 -1, i32 8)
|
||||
%res2 = add <16 x i32> %res, %res1
|
||||
ret <16 x i32> %res2
|
||||
}
|
||||
|
||||
declare <16 x i32> @llvm.x86.avx512.mask.cvttps2udq.512(<16 x float>, <16 x i32>, i16, i32)
|
||||
|
||||
define <16 x i32>@test_int_x86_avx512_mask_cvtt_ps2udq_512(<16 x float> %x0, <16 x i32> %x1, i16 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2udq_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovw %edi, %k1
|
||||
; CHECK-NEXT: vcvttps2udq %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vcvttps2udq {sae}, %zmm0, %zmm0
|
||||
; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <16 x i32> @llvm.x86.avx512.mask.cvttps2udq.512(<16 x float> %x0, <16 x i32> %x1, i16 %x2, i32 4)
|
||||
%res1 = call <16 x i32> @llvm.x86.avx512.mask.cvttps2udq.512(<16 x float> %x0, <16 x i32> %x1, i16 -1, i32 8)
|
||||
%res2 = add <16 x i32> %res, %res1
|
||||
ret <16 x i32> %res2
|
||||
}
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx --show-mc-encoding| FileCheck %s
|
||||
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512bw --show-mc-encoding| FileCheck %s
|
||||
|
||||
define i64 @test_pcmpeq_b(<64 x i8> %a, <64 x i8> %b) {
|
||||
; CHECK-LABEL: test_pcmpeq_b
|
||||
@ -304,28 +304,6 @@ define <8 x i32> @test_mask_ucmp_w_512(<32 x i16> %a0, <32 x i16> %a1, i32 %mask
|
||||
|
||||
declare i32 @llvm.x86.avx512.mask.ucmp.w.512(<32 x i16>, <32 x i16>, i32, i32) nounwind readnone
|
||||
|
||||
; CHECK-LABEL: test_x86_mask_blend_b_256
|
||||
; CHECK: vpblendmb
|
||||
define <32 x i8> @test_x86_mask_blend_b_256(i32 %a0, <32 x i8> %a1, <32 x i8> %a2) {
|
||||
%res = call <32 x i8> @llvm.x86.avx512.mask.blend.b.256(<32 x i8> %a1, <32 x i8> %a2, i32 %a0) ; <<32 x i8>> [#uses=1]
|
||||
ret <32 x i8> %res
|
||||
}
|
||||
declare <32 x i8> @llvm.x86.avx512.mask.blend.b.256(<32 x i8>, <32 x i8>, i32) nounwind readonly
|
||||
|
||||
; CHECK-LABEL: test_x86_mask_blend_w_256
|
||||
define <16 x i16> @test_x86_mask_blend_w_256(i16 %mask, <16 x i16> %a1, <16 x i16> %a2) {
|
||||
; CHECK: vpblendmw
|
||||
%res = call <16 x i16> @llvm.x86.avx512.mask.blend.w.256(<16 x i16> %a1, <16 x i16> %a2, i16 %mask) ; <<16 x i16>> [#uses=1]
|
||||
ret <16 x i16> %res
|
||||
}
|
||||
declare <16 x i16> @llvm.x86.avx512.mask.blend.w.256(<16 x i16>, <16 x i16>, i16) nounwind readonly
|
||||
|
||||
; CHECK-LABEL: test_x86_mask_blend_b_512
|
||||
; CHECK: vpblendmb
|
||||
define <64 x i8> @test_x86_mask_blend_b_512(i64 %a0, <64 x i8> %a1, <64 x i8> %a2) {
|
||||
%res = call <64 x i8> @llvm.x86.avx512.mask.blend.b.512(<64 x i8> %a1, <64 x i8> %a2, i64 %a0) ; <<64 x i8>> [#uses=1]
|
||||
ret <64 x i8> %res
|
||||
}
|
||||
declare <64 x i8> @llvm.x86.avx512.mask.blend.b.512(<64 x i8>, <64 x i8>, i64) nounwind readonly
|
||||
|
||||
; CHECK-LABEL: test_x86_mask_blend_w_512
|
||||
@ -336,21 +314,12 @@ define <32 x i16> @test_x86_mask_blend_w_512(i32 %mask, <32 x i16> %a1, <32 x i1
|
||||
}
|
||||
declare <32 x i16> @llvm.x86.avx512.mask.blend.w.512(<32 x i16>, <32 x i16>, i32) nounwind readonly
|
||||
|
||||
; CHECK-LABEL: test_x86_mask_blend_b_128
|
||||
; CHECK-LABEL: test_x86_mask_blend_b_512
|
||||
; CHECK: vpblendmb
|
||||
define <16 x i8> @test_x86_mask_blend_b_128(i16 %a0, <16 x i8> %a1, <16 x i8> %a2) {
|
||||
%res = call <16 x i8> @llvm.x86.avx512.mask.blend.b.128(<16 x i8> %a1, <16 x i8> %a2, i16 %a0) ; <<16 x i8>> [#uses=1]
|
||||
ret <16 x i8> %res
|
||||
define <64 x i8> @test_x86_mask_blend_b_512(i64 %a0, <64 x i8> %a1, <64 x i8> %a2) {
|
||||
%res = call <64 x i8> @llvm.x86.avx512.mask.blend.b.512(<64 x i8> %a1, <64 x i8> %a2, i64 %a0) ; <<64 x i8>> [#uses=1]
|
||||
ret <64 x i8> %res
|
||||
}
|
||||
declare <16 x i8> @llvm.x86.avx512.mask.blend.b.128(<16 x i8>, <16 x i8>, i16) nounwind readonly
|
||||
|
||||
; CHECK-LABEL: test_x86_mask_blend_w_128
|
||||
define <8 x i16> @test_x86_mask_blend_w_128(i8 %mask, <8 x i16> %a1, <8 x i16> %a2) {
|
||||
; CHECK: vpblendmw
|
||||
%res = call <8 x i16> @llvm.x86.avx512.mask.blend.w.128(<8 x i16> %a1, <8 x i16> %a2, i8 %mask) ; <<8 x i16>> [#uses=1]
|
||||
ret <8 x i16> %res
|
||||
}
|
||||
declare <8 x i16> @llvm.x86.avx512.mask.blend.w.128(<8 x i16>, <8 x i16>, i8) nounwind readonly
|
||||
|
||||
define <32 x i16> @test_mask_packs_epi32_rr_512(<16 x i32> %a, <16 x i32> %b) {
|
||||
;CHECK-LABEL: test_mask_packs_epi32_rr_512
|
||||
|
||||
@ -3763,6 +3763,38 @@ define <16 x i16>@test_int_x86_avx512_mask_pabs_w_256(<16 x i16> %x0, <16 x i16>
|
||||
ret <16 x i16> %res2
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test_x86_mask_blend_b_256
|
||||
; CHECK: vpblendmb
|
||||
define <32 x i8> @test_x86_mask_blend_b_256(i32 %a0, <32 x i8> %a1, <32 x i8> %a2) {
|
||||
%res = call <32 x i8> @llvm.x86.avx512.mask.blend.b.256(<32 x i8> %a1, <32 x i8> %a2, i32 %a0) ; <<32 x i8>> [#uses=1]
|
||||
ret <32 x i8> %res
|
||||
}
|
||||
declare <32 x i8> @llvm.x86.avx512.mask.blend.b.256(<32 x i8>, <32 x i8>, i32) nounwind readonly
|
||||
|
||||
; CHECK-LABEL: test_x86_mask_blend_w_256
|
||||
define <16 x i16> @test_x86_mask_blend_w_256(i16 %mask, <16 x i16> %a1, <16 x i16> %a2) {
|
||||
; CHECK: vpblendmw
|
||||
%res = call <16 x i16> @llvm.x86.avx512.mask.blend.w.256(<16 x i16> %a1, <16 x i16> %a2, i16 %mask) ; <<16 x i16>> [#uses=1]
|
||||
ret <16 x i16> %res
|
||||
}
|
||||
declare <16 x i16> @llvm.x86.avx512.mask.blend.w.256(<16 x i16>, <16 x i16>, i16) nounwind readonly
|
||||
|
||||
; CHECK-LABEL: test_x86_mask_blend_b_128
|
||||
; CHECK: vpblendmb
|
||||
define <16 x i8> @test_x86_mask_blend_b_128(i16 %a0, <16 x i8> %a1, <16 x i8> %a2) {
|
||||
%res = call <16 x i8> @llvm.x86.avx512.mask.blend.b.128(<16 x i8> %a1, <16 x i8> %a2, i16 %a0) ; <<16 x i8>> [#uses=1]
|
||||
ret <16 x i8> %res
|
||||
}
|
||||
declare <16 x i8> @llvm.x86.avx512.mask.blend.b.128(<16 x i8>, <16 x i8>, i16) nounwind readonly
|
||||
|
||||
; CHECK-LABEL: test_x86_mask_blend_w_128
|
||||
define <8 x i16> @test_x86_mask_blend_w_128(i8 %mask, <8 x i16> %a1, <8 x i16> %a2) {
|
||||
; CHECK: vpblendmw
|
||||
%res = call <8 x i16> @llvm.x86.avx512.mask.blend.w.128(<8 x i16> %a1, <8 x i16> %a2, i8 %mask) ; <<8 x i16>> [#uses=1]
|
||||
ret <8 x i16> %res
|
||||
}
|
||||
declare <8 x i16> @llvm.x86.avx512.mask.blend.w.128(<8 x i16>, <8 x i16>, i8) nounwind readonly
|
||||
|
||||
declare <8 x i16> @llvm.x86.avx512.mask.pmulhu.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)
|
||||
|
||||
; CHECK-LABEL: @test_int_x86_avx512_mask_pmulhu_w_128
|
||||
|
||||
194
test/CodeGen/X86/avx512dq-intrinsics.ll
Normal file
194
test/CodeGen/X86/avx512dq-intrinsics.ll
Normal file
@ -0,0 +1,194 @@
|
||||
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512dq | FileCheck %s
|
||||
|
||||
declare <8 x i64> @llvm.x86.avx512.mask.cvtpd2qq.512(<8 x double>, <8 x i64>, i8, i32)
|
||||
|
||||
define <8 x i64>@test_int_x86_avx512_mask_cvt_pd2qq_512(<8 x double> %x0, <8 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2qq_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtpd2qq {ru-sae}, %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtpd2qq {rn-sae}, %zmm0, %zmm0
|
||||
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x i64> @llvm.x86.avx512.mask.cvtpd2qq.512(<8 x double> %x0, <8 x i64> %x1, i8 %x2, i32 2)
|
||||
%res1 = call <8 x i64> @llvm.x86.avx512.mask.cvtpd2qq.512(<8 x double> %x0, <8 x i64> %x1, i8 -1, i32 0)
|
||||
%res2 = add <8 x i64> %res, %res1
|
||||
ret <8 x i64> %res2
|
||||
}
|
||||
|
||||
declare <8 x i64> @llvm.x86.avx512.mask.cvtpd2uqq.512(<8 x double>, <8 x i64>, i8, i32)
|
||||
|
||||
define <8 x i64>@test_int_x86_avx512_mask_cvt_pd2uqq_512(<8 x double> %x0, <8 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2uqq_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtpd2uqq {ru-sae}, %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtpd2uqq {rn-sae}, %zmm0, %zmm0
|
||||
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x i64> @llvm.x86.avx512.mask.cvtpd2uqq.512(<8 x double> %x0, <8 x i64> %x1, i8 %x2, i32 2)
|
||||
%res1 = call <8 x i64> @llvm.x86.avx512.mask.cvtpd2uqq.512(<8 x double> %x0, <8 x i64> %x1, i8 -1, i32 0)
|
||||
%res2 = add <8 x i64> %res, %res1
|
||||
ret <8 x i64> %res2
|
||||
}
|
||||
|
||||
declare <8 x i64> @llvm.x86.avx512.mask.cvtps2qq.512(<8 x float>, <8 x i64>, i8, i32)
|
||||
|
||||
define <8 x i64>@test_int_x86_avx512_mask_cvt_ps2qq_512(<8 x float> %x0, <8 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2qq_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtps2qq {ru-sae}, %ymm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtps2qq {rn-sae}, %ymm0, %zmm0
|
||||
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x i64> @llvm.x86.avx512.mask.cvtps2qq.512(<8 x float> %x0, <8 x i64> %x1, i8 %x2, i32 2)
|
||||
%res1 = call <8 x i64> @llvm.x86.avx512.mask.cvtps2qq.512(<8 x float> %x0, <8 x i64> %x1, i8 -1, i32 0)
|
||||
%res2 = add <8 x i64> %res, %res1
|
||||
ret <8 x i64> %res2
|
||||
}
|
||||
|
||||
declare <8 x i64> @llvm.x86.avx512.mask.cvtps2uqq.512(<8 x float>, <8 x i64>, i8, i32)
|
||||
|
||||
define <8 x i64>@test_int_x86_avx512_mask_cvt_ps2uqq_512(<8 x float> %x0, <8 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2uqq_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtps2uqq {ru-sae}, %ymm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtps2uqq {rn-sae}, %ymm0, %zmm0
|
||||
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x i64> @llvm.x86.avx512.mask.cvtps2uqq.512(<8 x float> %x0, <8 x i64> %x1, i8 %x2, i32 2)
|
||||
%res1 = call <8 x i64> @llvm.x86.avx512.mask.cvtps2uqq.512(<8 x float> %x0, <8 x i64> %x1, i8 -1, i32 0)
|
||||
%res2 = add <8 x i64> %res, %res1
|
||||
ret <8 x i64> %res2
|
||||
}
|
||||
|
||||
declare <8 x double> @llvm.x86.avx512.mask.cvtqq2pd.512(<8 x i64>, <8 x double>, i8, i32)
|
||||
|
||||
define <8 x double>@test_int_x86_avx512_mask_cvt_qq2pd_512(<8 x i64> %x0, <8 x double> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_qq2pd_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtqq2pd %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtqq2pd {rn-sae}, %zmm0, %zmm0
|
||||
; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x double> @llvm.x86.avx512.mask.cvtqq2pd.512(<8 x i64> %x0, <8 x double> %x1, i8 %x2, i32 4)
|
||||
%res1 = call <8 x double> @llvm.x86.avx512.mask.cvtqq2pd.512(<8 x i64> %x0, <8 x double> %x1, i8 -1, i32 0)
|
||||
%res2 = fadd <8 x double> %res, %res1
|
||||
ret <8 x double> %res2
|
||||
}
|
||||
|
||||
declare <8 x float> @llvm.x86.avx512.mask.cvtqq2ps.512(<8 x i64>, <8 x float>, i8, i32)
|
||||
|
||||
define <8 x float>@test_int_x86_avx512_mask_cvt_qq2ps_512(<8 x i64> %x0, <8 x float> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_qq2ps_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtqq2ps %zmm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvtqq2ps {rn-sae}, %zmm0, %ymm0
|
||||
; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x float> @llvm.x86.avx512.mask.cvtqq2ps.512(<8 x i64> %x0, <8 x float> %x1, i8 %x2, i32 4)
|
||||
%res1 = call <8 x float> @llvm.x86.avx512.mask.cvtqq2ps.512(<8 x i64> %x0, <8 x float> %x1, i8 -1, i32 0)
|
||||
%res2 = fadd <8 x float> %res, %res1
|
||||
ret <8 x float> %res2
|
||||
}
|
||||
|
||||
declare <8 x i64> @llvm.x86.avx512.mask.cvttpd2qq.512(<8 x double>, <8 x i64>, i8, i32)
|
||||
|
||||
define <8 x i64>@test_int_x86_avx512_mask_cvtt_pd2qq_512(<8 x double> %x0, <8 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2qq_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvttpd2qq %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vcvttpd2qq {sae}, %zmm0, %zmm0
|
||||
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x i64> @llvm.x86.avx512.mask.cvttpd2qq.512(<8 x double> %x0, <8 x i64> %x1, i8 %x2, i32 4)
|
||||
%res1 = call <8 x i64> @llvm.x86.avx512.mask.cvttpd2qq.512(<8 x double> %x0, <8 x i64> %x1, i8 -1, i32 8)
|
||||
%res2 = add <8 x i64> %res, %res1
|
||||
ret <8 x i64> %res2
|
||||
}
|
||||
|
||||
declare <8 x i64> @llvm.x86.avx512.mask.cvttpd2uqq.512(<8 x double>, <8 x i64>, i8, i32)
|
||||
|
||||
define <8 x i64>@test_int_x86_avx512_mask_cvtt_pd2uqq_512(<8 x double> %x0, <8 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2uqq_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvttpd2uqq %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vcvttpd2uqq {sae}, %zmm0, %zmm0
|
||||
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x i64> @llvm.x86.avx512.mask.cvttpd2uqq.512(<8 x double> %x0, <8 x i64> %x1, i8 %x2, i32 4)
|
||||
%res1 = call <8 x i64> @llvm.x86.avx512.mask.cvttpd2uqq.512(<8 x double> %x0, <8 x i64> %x1, i8 -1, i32 8)
|
||||
%res2 = add <8 x i64> %res, %res1
|
||||
ret <8 x i64> %res2
|
||||
}
|
||||
|
||||
declare <8 x i64> @llvm.x86.avx512.mask.cvttps2qq.512(<8 x float>, <8 x i64>, i8, i32)
|
||||
|
||||
define <8 x i64>@test_int_x86_avx512_mask_cvtt_ps2qq_512(<8 x float> %x0, <8 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2qq_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvttps2qq %ymm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vcvttps2qq {sae}, %ymm0, %zmm0
|
||||
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x i64> @llvm.x86.avx512.mask.cvttps2qq.512(<8 x float> %x0, <8 x i64> %x1, i8 %x2, i32 4)
|
||||
%res1 = call <8 x i64> @llvm.x86.avx512.mask.cvttps2qq.512(<8 x float> %x0, <8 x i64> %x1, i8 -1, i32 8)
|
||||
%res2 = add <8 x i64> %res, %res1
|
||||
ret <8 x i64> %res2
|
||||
}
|
||||
|
||||
declare <8 x i64> @llvm.x86.avx512.mask.cvttps2uqq.512(<8 x float>, <8 x i64>, i8, i32)
|
||||
|
||||
define <8 x i64>@test_int_x86_avx512_mask_cvtt_ps2uqq_512(<8 x float> %x0, <8 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2uqq_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvttps2uqq %ymm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vcvttps2uqq {sae}, %ymm0, %zmm0
|
||||
; CHECK-NEXT: vpaddq %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x i64> @llvm.x86.avx512.mask.cvttps2uqq.512(<8 x float> %x0, <8 x i64> %x1, i8 %x2, i32 4)
|
||||
%res1 = call <8 x i64> @llvm.x86.avx512.mask.cvttps2uqq.512(<8 x float> %x0, <8 x i64> %x1, i8 -1, i32 8)
|
||||
%res2 = add <8 x i64> %res, %res1
|
||||
ret <8 x i64> %res2
|
||||
}
|
||||
|
||||
declare <8 x double> @llvm.x86.avx512.mask.cvtuqq2pd.512(<8 x i64>, <8 x double>, i8, i32)
|
||||
|
||||
define <8 x double>@test_int_x86_avx512_mask_cvt_uqq2pd_512(<8 x i64> %x0, <8 x double> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_uqq2pd_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtuqq2pd %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtuqq2pd {rn-sae}, %zmm0, %zmm0
|
||||
; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x double> @llvm.x86.avx512.mask.cvtuqq2pd.512(<8 x i64> %x0, <8 x double> %x1, i8 %x2, i32 4)
|
||||
%res1 = call <8 x double> @llvm.x86.avx512.mask.cvtuqq2pd.512(<8 x i64> %x0, <8 x double> %x1, i8 -1, i32 0)
|
||||
%res2 = fadd <8 x double> %res, %res1
|
||||
ret <8 x double> %res2
|
||||
}
|
||||
|
||||
declare <8 x float> @llvm.x86.avx512.mask.cvtuqq2ps.512(<8 x i64>, <8 x float>, i8, i32)
|
||||
|
||||
define <8 x float>@test_int_x86_avx512_mask_cvt_uqq2ps_512(<8 x i64> %x0, <8 x float> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_uqq2ps_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtuqq2ps %zmm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvtuqq2ps {rn-sae}, %zmm0, %ymm0
|
||||
; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x float> @llvm.x86.avx512.mask.cvtuqq2ps.512(<8 x i64> %x0, <8 x float> %x1, i8 %x2, i32 4)
|
||||
%res1 = call <8 x float> @llvm.x86.avx512.mask.cvtuqq2ps.512(<8 x i64> %x0, <8 x float> %x1, i8 -1, i32 0)
|
||||
%res2 = fadd <8 x float> %res, %res1
|
||||
ret <8 x float> %res2
|
||||
}
|
||||
|
||||
@ -1134,7 +1134,7 @@ define <16 x float> @test_mask_xor_ps_rmb_512(<16 x float> %a, float* %ptr_b) {
|
||||
|
||||
define <16 x float> @test_mask_xor_ps_rmbk_512(<16 x float> %a, float* %ptr_b, <16 x float> %passThru, i16 %mask) {
|
||||
;CHECK-LABEL: test_mask_xor_ps_rmbk_512
|
||||
;CHECK: vxorps (%rdi){1to16}, %zmm0, %zmm1 {%k1} ## encoding: [0x62,0xf1,0x7c,0x59,0x57,0x0f]
|
||||
;CHECK: vxorps (%rdi){1to16}, %zmm0, %zmm1 {%k1}
|
||||
%q = load float, float* %ptr_b
|
||||
%vecinit.i = insertelement <16 x float> undef, float %q, i32 0
|
||||
%b = shufflevector <16 x float> %vecinit.i, <16 x float> undef, <16 x i32> zeroinitializer
|
||||
@ -1144,7 +1144,7 @@ define <16 x float> @test_mask_xor_ps_rmbk_512(<16 x float> %a, float* %ptr_b, <
|
||||
|
||||
define <16 x float> @test_mask_xor_ps_rmbkz_512(<16 x float> %a, float* %ptr_b, i16 %mask) {
|
||||
;CHECK-LABEL: test_mask_xor_ps_rmbkz_512
|
||||
;CHECK: vxorps (%rdi){1to16}, %zmm0, %zmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7c,0xd9,0x57,0x07]
|
||||
;CHECK: vxorps (%rdi){1to16}, %zmm0, %zmm0 {%k1} {z}
|
||||
%q = load float, float* %ptr_b
|
||||
%vecinit.i = insertelement <16 x float> undef, float %q, i32 0
|
||||
%b = shufflevector <16 x float> %vecinit.i, <16 x float> undef, <16 x i32> zeroinitializer
|
||||
@ -1152,4 +1152,388 @@ define <16 x float> @test_mask_xor_ps_rmbkz_512(<16 x float> %a, float* %ptr_b,
|
||||
ret <16 x float> %res
|
||||
}
|
||||
|
||||
declare <16 x float> @llvm.x86.avx512.mask.xor.ps.512(<16 x float>, <16 x float>, <16 x float>, i16)
|
||||
declare <16 x float> @llvm.x86.avx512.mask.xor.ps.512(<16 x float>, <16 x float>, <16 x float>, i16)
|
||||
|
||||
declare <2 x i64> @llvm.x86.avx512.mask.cvtpd2qq.128(<2 x double>, <2 x i64>, i8)
|
||||
|
||||
define <2 x i64>@test_int_x86_avx512_mask_cvt_pd2qq_128(<2 x double> %x0, <2 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2qq_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtpd2qq %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtpd2qq %xmm0, %xmm0
|
||||
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <2 x i64> @llvm.x86.avx512.mask.cvtpd2qq.128(<2 x double> %x0, <2 x i64> %x1, i8 %x2)
|
||||
%res1 = call <2 x i64> @llvm.x86.avx512.mask.cvtpd2qq.128(<2 x double> %x0, <2 x i64> %x1, i8 -1)
|
||||
%res2 = add <2 x i64> %res, %res1
|
||||
ret <2 x i64> %res2
|
||||
}
|
||||
|
||||
declare <4 x i64> @llvm.x86.avx512.mask.cvtpd2qq.256(<4 x double>, <4 x i64>, i8)
|
||||
|
||||
define <4 x i64>@test_int_x86_avx512_mask_cvt_pd2qq_256(<4 x double> %x0, <4 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2qq_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtpd2qq %ymm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvtpd2qq %ymm0, %ymm0
|
||||
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x i64> @llvm.x86.avx512.mask.cvtpd2qq.256(<4 x double> %x0, <4 x i64> %x1, i8 %x2)
|
||||
%res1 = call <4 x i64> @llvm.x86.avx512.mask.cvtpd2qq.256(<4 x double> %x0, <4 x i64> %x1, i8 -1)
|
||||
%res2 = add <4 x i64> %res, %res1
|
||||
ret <4 x i64> %res2
|
||||
}
|
||||
|
||||
declare <2 x i64> @llvm.x86.avx512.mask.cvtpd2uqq.128(<2 x double>, <2 x i64>, i8)
|
||||
|
||||
define <2 x i64>@test_int_x86_avx512_mask_cvt_pd2uqq_128(<2 x double> %x0, <2 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2uqq_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtpd2uqq %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtpd2uqq %xmm0, %xmm0
|
||||
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <2 x i64> @llvm.x86.avx512.mask.cvtpd2uqq.128(<2 x double> %x0, <2 x i64> %x1, i8 %x2)
|
||||
%res1 = call <2 x i64> @llvm.x86.avx512.mask.cvtpd2uqq.128(<2 x double> %x0, <2 x i64> %x1, i8 -1)
|
||||
%res2 = add <2 x i64> %res, %res1
|
||||
ret <2 x i64> %res2
|
||||
}
|
||||
|
||||
declare <4 x i64> @llvm.x86.avx512.mask.cvtpd2uqq.256(<4 x double>, <4 x i64>, i8)
|
||||
|
||||
define <4 x i64>@test_int_x86_avx512_mask_cvt_pd2uqq_256(<4 x double> %x0, <4 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2uqq_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtpd2uqq %ymm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvtpd2uqq %ymm0, %ymm0
|
||||
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x i64> @llvm.x86.avx512.mask.cvtpd2uqq.256(<4 x double> %x0, <4 x i64> %x1, i8 %x2)
|
||||
%res1 = call <4 x i64> @llvm.x86.avx512.mask.cvtpd2uqq.256(<4 x double> %x0, <4 x i64> %x1, i8 -1)
|
||||
%res2 = add <4 x i64> %res, %res1
|
||||
ret <4 x i64> %res2
|
||||
}
|
||||
|
||||
declare <2 x i64> @llvm.x86.avx512.mask.cvtps2qq.128(<4 x float>, <2 x i64>, i8)
|
||||
|
||||
define <2 x i64>@test_int_x86_avx512_mask_cvt_ps2qq_128(<4 x float> %x0, <2 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2qq_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtps2qq %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtps2qq %xmm0, %xmm0
|
||||
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <2 x i64> @llvm.x86.avx512.mask.cvtps2qq.128(<4 x float> %x0, <2 x i64> %x1, i8 %x2)
|
||||
%res1 = call <2 x i64> @llvm.x86.avx512.mask.cvtps2qq.128(<4 x float> %x0, <2 x i64> %x1, i8 -1)
|
||||
%res2 = add <2 x i64> %res, %res1
|
||||
ret <2 x i64> %res2
|
||||
}
|
||||
|
||||
declare <4 x i64> @llvm.x86.avx512.mask.cvtps2qq.256(<4 x float>, <4 x i64>, i8)
|
||||
|
||||
define <4 x i64>@test_int_x86_avx512_mask_cvt_ps2qq_256(<4 x float> %x0, <4 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2qq_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtps2qq %xmm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvtps2qq %xmm0, %ymm0
|
||||
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x i64> @llvm.x86.avx512.mask.cvtps2qq.256(<4 x float> %x0, <4 x i64> %x1, i8 %x2)
|
||||
%res1 = call <4 x i64> @llvm.x86.avx512.mask.cvtps2qq.256(<4 x float> %x0, <4 x i64> %x1, i8 -1)
|
||||
%res2 = add <4 x i64> %res, %res1
|
||||
ret <4 x i64> %res2
|
||||
}
|
||||
|
||||
declare <2 x i64> @llvm.x86.avx512.mask.cvtps2uqq.128(<4 x float>, <2 x i64>, i8)
|
||||
|
||||
define <2 x i64>@test_int_x86_avx512_mask_cvt_ps2uqq_128(<4 x float> %x0, <2 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2uqq_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtps2uqq %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtps2uqq %xmm0, %xmm0
|
||||
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <2 x i64> @llvm.x86.avx512.mask.cvtps2uqq.128(<4 x float> %x0, <2 x i64> %x1, i8 %x2)
|
||||
%res1 = call <2 x i64> @llvm.x86.avx512.mask.cvtps2uqq.128(<4 x float> %x0, <2 x i64> %x1, i8 -1)
|
||||
%res2 = add <2 x i64> %res, %res1
|
||||
ret <2 x i64> %res2
|
||||
}
|
||||
|
||||
declare <4 x i64> @llvm.x86.avx512.mask.cvtps2uqq.256(<4 x float>, <4 x i64>, i8)
|
||||
|
||||
define <4 x i64>@test_int_x86_avx512_mask_cvt_ps2uqq_256(<4 x float> %x0, <4 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2uqq_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtps2uqq %xmm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvtps2uqq %xmm0, %ymm0
|
||||
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x i64> @llvm.x86.avx512.mask.cvtps2uqq.256(<4 x float> %x0, <4 x i64> %x1, i8 %x2)
|
||||
%res1 = call <4 x i64> @llvm.x86.avx512.mask.cvtps2uqq.256(<4 x float> %x0, <4 x i64> %x1, i8 -1)
|
||||
%res2 = add <4 x i64> %res, %res1
|
||||
ret <4 x i64> %res2
|
||||
}
|
||||
|
||||
declare <2 x double> @llvm.x86.avx512.mask.cvtqq2pd.128(<2 x i64>, <2 x double>, i8)
|
||||
|
||||
define <2 x double>@test_int_x86_avx512_mask_cvt_qq2pd_128(<2 x i64> %x0, <2 x double> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_qq2pd_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtqq2pd %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtqq2pd %xmm0, %xmm0
|
||||
; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <2 x double> @llvm.x86.avx512.mask.cvtqq2pd.128(<2 x i64> %x0, <2 x double> %x1, i8 %x2)
|
||||
%res1 = call <2 x double> @llvm.x86.avx512.mask.cvtqq2pd.128(<2 x i64> %x0, <2 x double> %x1, i8 -1)
|
||||
%res2 = fadd <2 x double> %res, %res1
|
||||
ret <2 x double> %res2
|
||||
}
|
||||
|
||||
declare <4 x double> @llvm.x86.avx512.mask.cvtqq2pd.256(<4 x i64>, <4 x double>, i8)
|
||||
|
||||
define <4 x double>@test_int_x86_avx512_mask_cvt_qq2pd_256(<4 x i64> %x0, <4 x double> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_qq2pd_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtqq2pd %ymm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvtqq2pd %ymm0, %ymm0
|
||||
; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x double> @llvm.x86.avx512.mask.cvtqq2pd.256(<4 x i64> %x0, <4 x double> %x1, i8 %x2)
|
||||
%res1 = call <4 x double> @llvm.x86.avx512.mask.cvtqq2pd.256(<4 x i64> %x0, <4 x double> %x1, i8 -1)
|
||||
%res2 = fadd <4 x double> %res, %res1
|
||||
ret <4 x double> %res2
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.x86.avx512.mask.cvtqq2ps.128(<2 x i64>, <4 x float>, i8)
|
||||
|
||||
define <4 x float>@test_int_x86_avx512_mask_cvt_qq2ps_128(<2 x i64> %x0, <4 x float> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_qq2ps_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtqq2ps %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtqq2ps %xmm0, %xmm0
|
||||
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x float> @llvm.x86.avx512.mask.cvtqq2ps.128(<2 x i64> %x0, <4 x float> %x1, i8 %x2)
|
||||
%res1 = call <4 x float> @llvm.x86.avx512.mask.cvtqq2ps.128(<2 x i64> %x0, <4 x float> %x1, i8 -1)
|
||||
%res2 = fadd <4 x float> %res, %res1
|
||||
ret <4 x float> %res2
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.x86.avx512.mask.cvtqq2ps.256(<4 x i64>, <4 x float>, i8)
|
||||
|
||||
define <4 x float>@test_int_x86_avx512_mask_cvt_qq2ps_256(<4 x i64> %x0, <4 x float> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_qq2ps_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtqq2ps %ymm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtqq2ps %ymm0, %xmm0
|
||||
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x float> @llvm.x86.avx512.mask.cvtqq2ps.256(<4 x i64> %x0, <4 x float> %x1, i8 %x2)
|
||||
%res1 = call <4 x float> @llvm.x86.avx512.mask.cvtqq2ps.256(<4 x i64> %x0, <4 x float> %x1, i8 -1)
|
||||
%res2 = fadd <4 x float> %res, %res1
|
||||
ret <4 x float> %res2
|
||||
}
|
||||
|
||||
declare <2 x i64> @llvm.x86.avx512.mask.cvttpd2qq.128(<2 x double>, <2 x i64>, i8)
|
||||
|
||||
define <2 x i64>@test_int_x86_avx512_mask_cvtt_pd2qq_128(<2 x double> %x0, <2 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2qq_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvttpd2qq %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvttpd2qq %xmm0, %xmm0
|
||||
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <2 x i64> @llvm.x86.avx512.mask.cvttpd2qq.128(<2 x double> %x0, <2 x i64> %x1, i8 %x2)
|
||||
%res1 = call <2 x i64> @llvm.x86.avx512.mask.cvttpd2qq.128(<2 x double> %x0, <2 x i64> %x1, i8 -1)
|
||||
%res2 = add <2 x i64> %res, %res1
|
||||
ret <2 x i64> %res2
|
||||
}
|
||||
|
||||
declare <4 x i64> @llvm.x86.avx512.mask.cvttpd2qq.256(<4 x double>, <4 x i64>, i8)
|
||||
|
||||
define <4 x i64>@test_int_x86_avx512_mask_cvtt_pd2qq_256(<4 x double> %x0, <4 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2qq_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvttpd2qq %ymm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvttpd2qq %ymm0, %ymm0
|
||||
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x i64> @llvm.x86.avx512.mask.cvttpd2qq.256(<4 x double> %x0, <4 x i64> %x1, i8 %x2)
|
||||
%res1 = call <4 x i64> @llvm.x86.avx512.mask.cvttpd2qq.256(<4 x double> %x0, <4 x i64> %x1, i8 -1)
|
||||
%res2 = add <4 x i64> %res, %res1
|
||||
ret <4 x i64> %res2
|
||||
}
|
||||
|
||||
declare <2 x i64> @llvm.x86.avx512.mask.cvttpd2uqq.128(<2 x double>, <2 x i64>, i8)
|
||||
|
||||
define <2 x i64>@test_int_x86_avx512_mask_cvtt_pd2uqq_128(<2 x double> %x0, <2 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2uqq_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvttpd2uqq %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvttpd2uqq %xmm0, %xmm0
|
||||
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <2 x i64> @llvm.x86.avx512.mask.cvttpd2uqq.128(<2 x double> %x0, <2 x i64> %x1, i8 %x2)
|
||||
%res1 = call <2 x i64> @llvm.x86.avx512.mask.cvttpd2uqq.128(<2 x double> %x0, <2 x i64> %x1, i8 -1)
|
||||
%res2 = add <2 x i64> %res, %res1
|
||||
ret <2 x i64> %res2
|
||||
}
|
||||
|
||||
declare <4 x i64> @llvm.x86.avx512.mask.cvttpd2uqq.256(<4 x double>, <4 x i64>, i8)
|
||||
|
||||
define <4 x i64>@test_int_x86_avx512_mask_cvtt_pd2uqq_256(<4 x double> %x0, <4 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2uqq_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvttpd2uqq %ymm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvttpd2uqq %ymm0, %ymm0
|
||||
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x i64> @llvm.x86.avx512.mask.cvttpd2uqq.256(<4 x double> %x0, <4 x i64> %x1, i8 %x2)
|
||||
%res1 = call <4 x i64> @llvm.x86.avx512.mask.cvttpd2uqq.256(<4 x double> %x0, <4 x i64> %x1, i8 -1)
|
||||
%res2 = add <4 x i64> %res, %res1
|
||||
ret <4 x i64> %res2
|
||||
}
|
||||
|
||||
declare <2 x i64> @llvm.x86.avx512.mask.cvttps2qq.128(<4 x float>, <2 x i64>, i8)
|
||||
|
||||
define <2 x i64>@test_int_x86_avx512_mask_cvtt_ps2qq_128(<4 x float> %x0, <2 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2qq_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvttps2qq %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvttps2qq %xmm0, %xmm0
|
||||
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <2 x i64> @llvm.x86.avx512.mask.cvttps2qq.128(<4 x float> %x0, <2 x i64> %x1, i8 %x2)
|
||||
%res1 = call <2 x i64> @llvm.x86.avx512.mask.cvttps2qq.128(<4 x float> %x0, <2 x i64> %x1, i8 -1)
|
||||
%res2 = add <2 x i64> %res, %res1
|
||||
ret <2 x i64> %res2
|
||||
}
|
||||
|
||||
declare <4 x i64> @llvm.x86.avx512.mask.cvttps2qq.256(<4 x float>, <4 x i64>, i8)
|
||||
|
||||
define <4 x i64>@test_int_x86_avx512_mask_cvtt_ps2qq_256(<4 x float> %x0, <4 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2qq_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvttps2qq %xmm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvttps2qq %xmm0, %ymm0
|
||||
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x i64> @llvm.x86.avx512.mask.cvttps2qq.256(<4 x float> %x0, <4 x i64> %x1, i8 %x2)
|
||||
%res1 = call <4 x i64> @llvm.x86.avx512.mask.cvttps2qq.256(<4 x float> %x0, <4 x i64> %x1, i8 -1)
|
||||
%res2 = add <4 x i64> %res, %res1
|
||||
ret <4 x i64> %res2
|
||||
}
|
||||
|
||||
declare <2 x double> @llvm.x86.avx512.mask.cvtuqq2pd.128(<2 x i64>, <2 x double>, i8)
|
||||
|
||||
define <2 x double>@test_int_x86_avx512_mask_cvt_uqq2pd_128(<2 x i64> %x0, <2 x double> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_uqq2pd_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtuqq2pd %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtuqq2pd %xmm0, %xmm0
|
||||
; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <2 x double> @llvm.x86.avx512.mask.cvtuqq2pd.128(<2 x i64> %x0, <2 x double> %x1, i8 %x2)
|
||||
%res1 = call <2 x double> @llvm.x86.avx512.mask.cvtuqq2pd.128(<2 x i64> %x0, <2 x double> %x1, i8 -1)
|
||||
%res2 = fadd <2 x double> %res, %res1
|
||||
ret <2 x double> %res2
|
||||
}
|
||||
|
||||
declare <4 x double> @llvm.x86.avx512.mask.cvtuqq2pd.256(<4 x i64>, <4 x double>, i8)
|
||||
|
||||
define <4 x double>@test_int_x86_avx512_mask_cvt_uqq2pd_256(<4 x i64> %x0, <4 x double> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_uqq2pd_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtuqq2pd %ymm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvtuqq2pd %ymm0, %ymm0
|
||||
; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x double> @llvm.x86.avx512.mask.cvtuqq2pd.256(<4 x i64> %x0, <4 x double> %x1, i8 %x2)
|
||||
%res1 = call <4 x double> @llvm.x86.avx512.mask.cvtuqq2pd.256(<4 x i64> %x0, <4 x double> %x1, i8 -1)
|
||||
%res2 = fadd <4 x double> %res, %res1
|
||||
ret <4 x double> %res2
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.x86.avx512.mask.cvtuqq2ps.128(<2 x i64>, <4 x float>, i8)
|
||||
|
||||
define <4 x float>@test_int_x86_avx512_mask_cvt_uqq2ps_128(<2 x i64> %x0, <4 x float> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_uqq2ps_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtuqq2ps %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtuqq2ps %xmm0, %xmm0
|
||||
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x float> @llvm.x86.avx512.mask.cvtuqq2ps.128(<2 x i64> %x0, <4 x float> %x1, i8 %x2)
|
||||
%res1 = call <4 x float> @llvm.x86.avx512.mask.cvtuqq2ps.128(<2 x i64> %x0, <4 x float> %x1, i8 -1)
|
||||
%res2 = fadd <4 x float> %res, %res1
|
||||
ret <4 x float> %res2
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.x86.avx512.mask.cvtuqq2ps.256(<4 x i64>, <4 x float>, i8)
|
||||
|
||||
define <4 x float>@test_int_x86_avx512_mask_cvt_uqq2ps_256(<4 x i64> %x0, <4 x float> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_uqq2ps_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvtuqq2ps %ymm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtuqq2ps %ymm0, %xmm0
|
||||
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x float> @llvm.x86.avx512.mask.cvtuqq2ps.256(<4 x i64> %x0, <4 x float> %x1, i8 %x2)
|
||||
%res1 = call <4 x float> @llvm.x86.avx512.mask.cvtuqq2ps.256(<4 x i64> %x0, <4 x float> %x1, i8 -1)
|
||||
%res2 = fadd <4 x float> %res, %res1
|
||||
ret <4 x float> %res2
|
||||
}
|
||||
|
||||
declare <2 x i64> @llvm.x86.avx512.mask.cvttps2uqq.128(<4 x float>, <2 x i64>, i8)
|
||||
|
||||
define <2 x i64>@test_int_x86_avx512_mask_cvtt_ps2uqq_128(<4 x float> %x0, <2 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2uqq_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvttps2uqq %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvttps2uqq %xmm0, %xmm0
|
||||
; CHECK-NEXT: vpaddq %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <2 x i64> @llvm.x86.avx512.mask.cvttps2uqq.128(<4 x float> %x0, <2 x i64> %x1, i8 %x2)
|
||||
%res1 = call <2 x i64> @llvm.x86.avx512.mask.cvttps2uqq.128(<4 x float> %x0, <2 x i64> %x1, i8 -1)
|
||||
%res2 = add <2 x i64> %res, %res1
|
||||
ret <2 x i64> %res2
|
||||
}
|
||||
|
||||
declare <4 x i64> @llvm.x86.avx512.mask.cvttps2uqq.256(<4 x float>, <4 x i64>, i8)
|
||||
|
||||
define <4 x i64>@test_int_x86_avx512_mask_cvtt_ps2uqq_256(<4 x float> %x0, <4 x i64> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2uqq_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovb %edi, %k1
|
||||
; CHECK-NEXT: vcvttps2uqq %xmm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvttps2uqq %xmm0, %ymm0
|
||||
; CHECK-NEXT: vpaddq %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x i64> @llvm.x86.avx512.mask.cvttps2uqq.256(<4 x float> %x0, <4 x i64> %x1, i8 %x2)
|
||||
%res1 = call <4 x i64> @llvm.x86.avx512.mask.cvttps2uqq.256(<4 x float> %x0, <4 x i64> %x1, i8 -1)
|
||||
%res2 = add <4 x i64> %res, %res1
|
||||
ret <4 x i64> %res2
|
||||
}
|
||||
|
||||
@ -3003,4 +3003,481 @@ define <8 x float>@test_int_x86_avx512_mask_scalef_ps_256(<8 x float> %x0, <8 x
|
||||
%res1 = call <8 x float> @llvm.x86.avx512.mask.scalef.ps.256(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, i8 -1)
|
||||
%res2 = fadd <8 x float> %res, %res1
|
||||
ret <8 x float> %res2
|
||||
}
|
||||
}
|
||||
|
||||
declare <2 x double> @llvm.x86.avx512.mask.cvtdq2pd.128(<4 x i32>, <2 x double>, i8)
|
||||
|
||||
define <2 x double>@test_int_x86_avx512_mask_cvt_dq2pd_128(<4 x i32> %x0, <2 x double> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_dq2pd_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtdq2pd %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtdq2pd %xmm0, %xmm0
|
||||
; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <2 x double> @llvm.x86.avx512.mask.cvtdq2pd.128(<4 x i32> %x0, <2 x double> %x1, i8 %x2)
|
||||
%res1 = call <2 x double> @llvm.x86.avx512.mask.cvtdq2pd.128(<4 x i32> %x0, <2 x double> %x1, i8 -1)
|
||||
%res2 = fadd <2 x double> %res, %res1
|
||||
ret <2 x double> %res2
|
||||
}
|
||||
|
||||
declare <4 x double> @llvm.x86.avx512.mask.cvtdq2pd.256(<4 x i32>, <4 x double>, i8)
|
||||
|
||||
define <4 x double>@test_int_x86_avx512_mask_cvt_dq2pd_256(<4 x i32> %x0, <4 x double> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_dq2pd_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtdq2pd %xmm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvtdq2pd %xmm0, %ymm0
|
||||
; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x double> @llvm.x86.avx512.mask.cvtdq2pd.256(<4 x i32> %x0, <4 x double> %x1, i8 %x2)
|
||||
%res1 = call <4 x double> @llvm.x86.avx512.mask.cvtdq2pd.256(<4 x i32> %x0, <4 x double> %x1, i8 -1)
|
||||
%res2 = fadd <4 x double> %res, %res1
|
||||
ret <4 x double> %res2
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.x86.avx512.mask.cvtdq2ps.128(<4 x i32>, <4 x float>, i8)
|
||||
|
||||
define <4 x float>@test_int_x86_avx512_mask_cvt_dq2ps_128(<4 x i32> %x0, <4 x float> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_dq2ps_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm0
|
||||
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x float> @llvm.x86.avx512.mask.cvtdq2ps.128(<4 x i32> %x0, <4 x float> %x1, i8 %x2)
|
||||
%res1 = call <4 x float> @llvm.x86.avx512.mask.cvtdq2ps.128(<4 x i32> %x0, <4 x float> %x1, i8 -1)
|
||||
%res2 = fadd <4 x float> %res, %res1
|
||||
ret <4 x float> %res2
|
||||
}
|
||||
|
||||
declare <8 x float> @llvm.x86.avx512.mask.cvtdq2ps.256(<8 x i32>, <8 x float>, i8)
|
||||
|
||||
define <8 x float>@test_int_x86_avx512_mask_cvt_dq2ps_256(<8 x i32> %x0, <8 x float> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_dq2ps_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtdq2ps %ymm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvtdq2ps %ymm0, %ymm0
|
||||
; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x float> @llvm.x86.avx512.mask.cvtdq2ps.256(<8 x i32> %x0, <8 x float> %x1, i8 %x2)
|
||||
%res1 = call <8 x float> @llvm.x86.avx512.mask.cvtdq2ps.256(<8 x i32> %x0, <8 x float> %x1, i8 -1)
|
||||
%res2 = fadd <8 x float> %res, %res1
|
||||
ret <8 x float> %res2
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.128(<2 x double>, <4 x i32>, i8)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_cvt_pd2dq_128(<2 x double> %x0, <4 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2dq_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtpd2dq %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtpd2dq %xmm0, %xmm0
|
||||
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.128(<2 x double> %x0, <4 x i32> %x1, i8 %x2)
|
||||
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.128(<2 x double> %x0, <4 x i32> %x1, i8 -1)
|
||||
%res2 = add <4 x i32> %res, %res1
|
||||
ret <4 x i32> %res2
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.256(<4 x double>, <4 x i32>, i8)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_cvt_pd2dq_256(<4 x double> %x0, <4 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2dq_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtpd2dq %ymm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtpd2dq %ymm0, %xmm0
|
||||
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.256(<4 x double> %x0, <4 x i32> %x1, i8 %x2)
|
||||
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2dq.256(<4 x double> %x0, <4 x i32> %x1, i8 -1)
|
||||
%res2 = add <4 x i32> %res, %res1
|
||||
ret <4 x i32> %res2
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.x86.avx512.mask.cvtpd2ps.256(<4 x double>, <4 x float>, i8)
|
||||
|
||||
define <4 x float>@test_int_x86_avx512_mask_cvt_pd2ps_256(<4 x double> %x0, <4 x float> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2ps_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtpd2ps %ymm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtpd2ps %ymm0, %xmm0
|
||||
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps.256(<4 x double> %x0, <4 x float> %x1, i8 %x2)
|
||||
%res1 = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps.256(<4 x double> %x0, <4 x float> %x1, i8 -1)
|
||||
%res2 = fadd <4 x float> %res, %res1
|
||||
ret <4 x float> %res2
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.x86.avx512.mask.cvtpd2ps(<2 x double>, <4 x float>, i8)
|
||||
|
||||
define <4 x float>@test_int_x86_avx512_mask_cvt_pd2ps(<2 x double> %x0, <4 x float> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2ps:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtpd2ps %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtpd2ps %xmm0, %xmm0
|
||||
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps(<2 x double> %x0, <4 x float> %x1, i8 %x2)
|
||||
%res1 = call <4 x float> @llvm.x86.avx512.mask.cvtpd2ps(<2 x double> %x0, <4 x float> %x1, i8 -1)
|
||||
%res2 = fadd <4 x float> %res, %res1
|
||||
ret <4 x float> %res2
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.128(<2 x double>, <4 x i32>, i8)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_cvt_pd2udq_128(<2 x double> %x0, <4 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2udq_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtpd2udq %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtpd2udq %xmm0, %xmm0
|
||||
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.128(<2 x double> %x0, <4 x i32> %x1, i8 %x2)
|
||||
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.128(<2 x double> %x0, <4 x i32> %x1, i8 -1)
|
||||
%res2 = add <4 x i32> %res, %res1
|
||||
ret <4 x i32> %res2
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.256(<4 x double>, <4 x i32>, i8)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_cvt_pd2udq_256(<4 x double> %x0, <4 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_pd2udq_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtpd2udq %ymm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtpd2udq %ymm0, %xmm0
|
||||
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.256(<4 x double> %x0, <4 x i32> %x1, i8 %x2)
|
||||
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvtpd2udq.256(<4 x double> %x0, <4 x i32> %x1, i8 -1)
|
||||
%res2 = add <4 x i32> %res, %res1
|
||||
ret <4 x i32> %res2
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.cvtps2dq.128(<4 x float>, <4 x i32>, i8)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_cvt_ps2dq_128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2dq_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtps2dq %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtps2dq %xmm0, %xmm0
|
||||
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x i32> @llvm.x86.avx512.mask.cvtps2dq.128(<4 x float> %x0, <4 x i32> %x1, i8 %x2)
|
||||
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvtps2dq.128(<4 x float> %x0, <4 x i32> %x1, i8 -1)
|
||||
%res2 = add <4 x i32> %res, %res1
|
||||
ret <4 x i32> %res2
|
||||
}
|
||||
|
||||
declare <8 x i32> @llvm.x86.avx512.mask.cvtps2dq.256(<8 x float>, <8 x i32>, i8)
|
||||
|
||||
define <8 x i32>@test_int_x86_avx512_mask_cvt_ps2dq_256(<8 x float> %x0, <8 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2dq_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtps2dq %ymm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvtps2dq %ymm0, %ymm0
|
||||
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x i32> @llvm.x86.avx512.mask.cvtps2dq.256(<8 x float> %x0, <8 x i32> %x1, i8 %x2)
|
||||
%res1 = call <8 x i32> @llvm.x86.avx512.mask.cvtps2dq.256(<8 x float> %x0, <8 x i32> %x1, i8 -1)
|
||||
%res2 = add <8 x i32> %res, %res1
|
||||
ret <8 x i32> %res2
|
||||
}
|
||||
|
||||
declare <2 x double> @llvm.x86.avx512.mask.cvtps2pd.128(<4 x float>, <2 x double>, i8)
|
||||
|
||||
define <2 x double>@test_int_x86_avx512_mask_cvt_ps2pd_128(<4 x float> %x0, <2 x double> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2pd_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtps2pd %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtps2pd %xmm0, %xmm0
|
||||
; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <2 x double> @llvm.x86.avx512.mask.cvtps2pd.128(<4 x float> %x0, <2 x double> %x1, i8 %x2)
|
||||
%res1 = call <2 x double> @llvm.x86.avx512.mask.cvtps2pd.128(<4 x float> %x0, <2 x double> %x1, i8 -1)
|
||||
%res2 = fadd <2 x double> %res, %res1
|
||||
ret <2 x double> %res2
|
||||
}
|
||||
|
||||
declare <4 x double> @llvm.x86.avx512.mask.cvtps2pd.256(<4 x float>, <4 x double>, i8)
|
||||
|
||||
define <4 x double>@test_int_x86_avx512_mask_cvt_ps2pd_256(<4 x float> %x0, <4 x double> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2pd_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtps2pd %xmm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvtps2pd %xmm0, %ymm0
|
||||
; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x double> @llvm.x86.avx512.mask.cvtps2pd.256(<4 x float> %x0, <4 x double> %x1, i8 %x2)
|
||||
%res1 = call <4 x double> @llvm.x86.avx512.mask.cvtps2pd.256(<4 x float> %x0, <4 x double> %x1, i8 -1)
|
||||
%res2 = fadd <4 x double> %res, %res1
|
||||
ret <4 x double> %res2
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.cvtps2udq.128(<4 x float>, <4 x i32>, i8)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_cvt_ps2udq_128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2udq_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtps2udq %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtps2udq %xmm0, %xmm0
|
||||
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x i32> @llvm.x86.avx512.mask.cvtps2udq.128(<4 x float> %x0, <4 x i32> %x1, i8 %x2)
|
||||
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvtps2udq.128(<4 x float> %x0, <4 x i32> %x1, i8 -1)
|
||||
%res2 = add <4 x i32> %res, %res1
|
||||
ret <4 x i32> %res2
|
||||
}
|
||||
|
||||
declare <8 x i32> @llvm.x86.avx512.mask.cvtps2udq.256(<8 x float>, <8 x i32>, i8)
|
||||
|
||||
define <8 x i32>@test_int_x86_avx512_mask_cvt_ps2udq_256(<8 x float> %x0, <8 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_ps2udq_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtps2udq %ymm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvtps2udq %ymm0, %ymm0
|
||||
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x i32> @llvm.x86.avx512.mask.cvtps2udq.256(<8 x float> %x0, <8 x i32> %x1, i8 %x2)
|
||||
%res1 = call <8 x i32> @llvm.x86.avx512.mask.cvtps2udq.256(<8 x float> %x0, <8 x i32> %x1, i8 -1)
|
||||
%res2 = add <8 x i32> %res, %res1
|
||||
ret <8 x i32> %res2
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.128(<2 x double>, <4 x i32>, i8)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_cvtt_pd2dq_128(<2 x double> %x0, <4 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2dq_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvttpd2dq %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvttpd2dq %xmm0, %xmm0
|
||||
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.128(<2 x double> %x0, <4 x i32> %x1, i8 %x2)
|
||||
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.128(<2 x double> %x0, <4 x i32> %x1, i8 -1)
|
||||
%res2 = add <4 x i32> %res, %res1
|
||||
ret <4 x i32> %res2
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.256(<4 x double>, <4 x i32>, i8)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_cvtt_pd2dq_256(<4 x double> %x0, <4 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2dq_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvttpd2dq %ymm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvttpd2dq %ymm0, %xmm0
|
||||
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.256(<4 x double> %x0, <4 x i32> %x1, i8 %x2)
|
||||
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2dq.256(<4 x double> %x0, <4 x i32> %x1, i8 -1)
|
||||
%res2 = add <4 x i32> %res, %res1
|
||||
ret <4 x i32> %res2
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.128(<2 x double>, <4 x i32>, i8)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_cvtt_pd2udq_128(<2 x double> %x0, <4 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2udq_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvttpd2udq %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvttpd2udq %xmm0, %xmm0
|
||||
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.128(<2 x double> %x0, <4 x i32> %x1, i8 %x2)
|
||||
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.128(<2 x double> %x0, <4 x i32> %x1, i8 -1)
|
||||
%res2 = add <4 x i32> %res, %res1
|
||||
ret <4 x i32> %res2
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.256(<4 x double>, <4 x i32>, i8)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_cvtt_pd2udq_256(<4 x double> %x0, <4 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_pd2udq_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvttpd2udq %ymm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvttpd2udq %ymm0, %xmm0
|
||||
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.256(<4 x double> %x0, <4 x i32> %x1, i8 %x2)
|
||||
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvttpd2udq.256(<4 x double> %x0, <4 x i32> %x1, i8 -1)
|
||||
%res2 = add <4 x i32> %res, %res1
|
||||
ret <4 x i32> %res2
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.cvttps2dq.128(<4 x float>, <4 x i32>, i8)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_cvtt_ps2dq_128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2dq_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvttps2dq %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvttps2dq %xmm0, %xmm0
|
||||
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x i32> @llvm.x86.avx512.mask.cvttps2dq.128(<4 x float> %x0, <4 x i32> %x1, i8 %x2)
|
||||
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvttps2dq.128(<4 x float> %x0, <4 x i32> %x1, i8 -1)
|
||||
%res2 = add <4 x i32> %res, %res1
|
||||
ret <4 x i32> %res2
|
||||
}
|
||||
|
||||
declare <8 x i32> @llvm.x86.avx512.mask.cvttps2dq.256(<8 x float>, <8 x i32>, i8)
|
||||
|
||||
define <8 x i32>@test_int_x86_avx512_mask_cvtt_ps2dq_256(<8 x float> %x0, <8 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2dq_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvttps2dq %ymm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvttps2dq %ymm0, %ymm0
|
||||
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x i32> @llvm.x86.avx512.mask.cvttps2dq.256(<8 x float> %x0, <8 x i32> %x1, i8 %x2)
|
||||
%res1 = call <8 x i32> @llvm.x86.avx512.mask.cvttps2dq.256(<8 x float> %x0, <8 x i32> %x1, i8 -1)
|
||||
%res2 = add <8 x i32> %res, %res1
|
||||
ret <8 x i32> %res2
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.x86.avx512.mask.cvttps2udq.128(<4 x float>, <4 x i32>, i8)
|
||||
|
||||
define <4 x i32>@test_int_x86_avx512_mask_cvtt_ps2udq_128(<4 x float> %x0, <4 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2udq_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvttps2udq %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvttps2udq %xmm0, %xmm0
|
||||
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x i32> @llvm.x86.avx512.mask.cvttps2udq.128(<4 x float> %x0, <4 x i32> %x1, i8 %x2)
|
||||
%res1 = call <4 x i32> @llvm.x86.avx512.mask.cvttps2udq.128(<4 x float> %x0, <4 x i32> %x1, i8 -1)
|
||||
%res2 = add <4 x i32> %res, %res1
|
||||
ret <4 x i32> %res2
|
||||
}
|
||||
|
||||
declare <8 x i32> @llvm.x86.avx512.mask.cvttps2udq.256(<8 x float>, <8 x i32>, i8)
|
||||
|
||||
define <8 x i32>@test_int_x86_avx512_mask_cvtt_ps2udq_256(<8 x float> %x0, <8 x i32> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvtt_ps2udq_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvttps2udq %ymm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvttps2udq %ymm0, %ymm0
|
||||
; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x i32> @llvm.x86.avx512.mask.cvttps2udq.256(<8 x float> %x0, <8 x i32> %x1, i8 %x2)
|
||||
%res1 = call <8 x i32> @llvm.x86.avx512.mask.cvttps2udq.256(<8 x float> %x0, <8 x i32> %x1, i8 -1)
|
||||
%res2 = add <8 x i32> %res, %res1
|
||||
ret <8 x i32> %res2
|
||||
}
|
||||
|
||||
declare <2 x double> @llvm.x86.avx512.mask.cvtudq2pd.128(<4 x i32>, <2 x double>, i8)
|
||||
|
||||
define <2 x double>@test_int_x86_avx512_mask_cvt_udq2pd_128(<4 x i32> %x0, <2 x double> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_udq2pd_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtudq2pd %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtudq2pd %xmm0, %xmm0
|
||||
; CHECK-NEXT: vaddpd %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <2 x double> @llvm.x86.avx512.mask.cvtudq2pd.128(<4 x i32> %x0, <2 x double> %x1, i8 %x2)
|
||||
%res1 = call <2 x double> @llvm.x86.avx512.mask.cvtudq2pd.128(<4 x i32> %x0, <2 x double> %x1, i8 -1)
|
||||
%res2 = fadd <2 x double> %res, %res1
|
||||
ret <2 x double> %res2
|
||||
}
|
||||
|
||||
declare <4 x double> @llvm.x86.avx512.mask.cvtudq2pd.256(<4 x i32>, <4 x double>, i8)
|
||||
|
||||
define <4 x double>@test_int_x86_avx512_mask_cvt_udq2pd_256(<4 x i32> %x0, <4 x double> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_udq2pd_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtudq2pd %xmm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvtudq2pd %xmm0, %ymm0
|
||||
; CHECK-NEXT: vaddpd %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x double> @llvm.x86.avx512.mask.cvtudq2pd.256(<4 x i32> %x0, <4 x double> %x1, i8 %x2)
|
||||
%res1 = call <4 x double> @llvm.x86.avx512.mask.cvtudq2pd.256(<4 x i32> %x0, <4 x double> %x1, i8 -1)
|
||||
%res2 = fadd <4 x double> %res, %res1
|
||||
ret <4 x double> %res2
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.x86.avx512.mask.cvtudq2ps.128(<4 x i32>, <4 x float>, i8)
|
||||
|
||||
define <4 x float>@test_int_x86_avx512_mask_cvt_udq2ps_128(<4 x i32> %x0, <4 x float> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_udq2ps_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtudq2ps %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: vcvtudq2ps %xmm0, %xmm0
|
||||
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x float> @llvm.x86.avx512.mask.cvtudq2ps.128(<4 x i32> %x0, <4 x float> %x1, i8 %x2)
|
||||
%res1 = call <4 x float> @llvm.x86.avx512.mask.cvtudq2ps.128(<4 x i32> %x0, <4 x float> %x1, i8 -1)
|
||||
%res2 = fadd <4 x float> %res, %res1
|
||||
ret <4 x float> %res2
|
||||
}
|
||||
|
||||
declare <8 x float> @llvm.x86.avx512.mask.cvtudq2ps.256(<8 x i32>, <8 x float>, i8)
|
||||
|
||||
define <8 x float>@test_int_x86_avx512_mask_cvt_udq2ps_256(<8 x i32> %x0, <8 x float> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_cvt_udq2ps_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vcvtudq2ps %ymm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: vcvtudq2ps %ymm0, %ymm0
|
||||
; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x float> @llvm.x86.avx512.mask.cvtudq2ps.256(<8 x i32> %x0, <8 x float> %x1, i8 %x2)
|
||||
%res1 = call <8 x float> @llvm.x86.avx512.mask.cvtudq2ps.256(<8 x i32> %x0, <8 x float> %x1, i8 -1)
|
||||
%res2 = fadd <8 x float> %res, %res1
|
||||
ret <8 x float> %res2
|
||||
}
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user