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Modify the TargetLowering::getPackedTypeBreakdown method to also return the
unpromoted element type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27273 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -178,10 +178,13 @@ public:
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/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
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/// Similarly, <2 x long> turns into 4 MVT::i32 values with both PPC and X86.
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///
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/// This method returns the number and type of the resultant breakdown.
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/// This method returns the number of registers needed, and the VT for each
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/// register. It also returns the VT of the PackedType elements before they
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/// are promoted/expanded.
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///
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MVT::ValueType getPackedTypeBreakdown(const PackedType *PTy,
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unsigned &NE) const;
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unsigned getPackedTypeBreakdown(const PackedType *PTy,
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MVT::ValueType &PTyElementVT,
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MVT::ValueType &PTyLegalElementVT) const;
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typedef std::vector<double>::const_iterator legal_fpimm_iterator;
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legal_fpimm_iterator legal_fpimm_begin() const {
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@ -148,11 +148,13 @@ const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
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///
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/// This method returns the number and type of the resultant breakdown.
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///
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MVT::ValueType TargetLowering::getPackedTypeBreakdown(const PackedType *PTy,
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unsigned &NumVals) const {
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unsigned TargetLowering::getPackedTypeBreakdown(const PackedType *PTy,
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MVT::ValueType &PTyElementVT,
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MVT::ValueType &PTyLegalElementVT) const {
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// Figure out the right, legal destination reg to copy into.
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unsigned NumElts = PTy->getNumElements();
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MVT::ValueType EltTy = getValueType(PTy->getElementType());
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PTyElementVT = EltTy;
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unsigned NumVectorRegs = 1;
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@ -170,13 +172,14 @@ MVT::ValueType TargetLowering::getPackedTypeBreakdown(const PackedType *PTy,
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VT = getVectorType(EltTy, NumElts);
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MVT::ValueType DestVT = getTypeToTransformTo(VT);
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PTyLegalElementVT = DestVT;
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if (DestVT < VT) {
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// Value is expanded, e.g. i64 -> i16.
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NumVals = NumVectorRegs*(MVT::getSizeInBits(VT)/MVT::getSizeInBits(DestVT));
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return NumVectorRegs*(MVT::getSizeInBits(VT)/MVT::getSizeInBits(DestVT));
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} else {
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// Otherwise, promotion or legal types use the same number of registers as
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// the vector decimated to the appropriate level.
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NumVals = NumVectorRegs;
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return NumVectorRegs;
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}
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return DestVT;
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