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Replace uint16_t with the MCPhysReg typedef in many places. A lot of physical register arrays already use this typedef.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254843 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2015-12-05 07:13:35 +00:00
parent 83f50fab53
commit 79402ee6f9
21 changed files with 98 additions and 96 deletions
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2
include/llvm/CodeGen/CallingConvLower.h
View File

@ -369,7 +369,7 @@ public:
/// AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive
/// registers. If this is not possible, return zero. Otherwise, return the first
/// register of the block that were allocated, marking the entire block as allocated.
unsigned AllocateRegBlock(ArrayRef<uint16_t> Regs, unsigned RegsRequired) {
unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) {
if (RegsRequired > Regs.size())
return 0;

28
include/llvm/MC/MCInstrDesc.h
View File

@ -15,12 +15,12 @@
#ifndef LLVM_MC_MCINSTRDESC_H
#define LLVM_MC_MCINSTRDESC_H
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/DataTypes.h"
#include <string>
namespace llvm {
class MCInst;
class MCRegisterInfo;
class MCSubtargetInfo;
class FeatureBitset;
@ -137,16 +137,16 @@ enum Flag {
/// directly to describe itself.
class MCInstrDesc {
public:
unsigned short Opcode; // The opcode number
unsigned short NumOperands; // Num of args (may be more if variable_ops)
unsigned char NumDefs; // Num of args that are definitions
unsigned char Size; // Number of bytes in encoding.
unsigned short SchedClass; // enum identifying instr sched class
uint64_t Flags; // Flags identifying machine instr class
uint64_t TSFlags; // Target Specific Flag values
const uint16_t *ImplicitUses; // Registers implicitly read by this instr
const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr
const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
unsigned short Opcode; // The opcode number
unsigned short NumOperands; // Num of args (may be more if variable_ops)
unsigned char NumDefs; // Num of args that are definitions
unsigned char Size; // Number of bytes in encoding.
unsigned short SchedClass; // enum identifying instr sched class
uint64_t Flags; // Flags identifying machine instr class
uint64_t TSFlags; // Target Specific Flag values
const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr
const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr
const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
// Subtarget feature that this is deprecated on, if any
// -1 implies this is not deprecated by any single feature. It may still be
// deprecated due to a "complex" reason, below.
@ -472,7 +472,7 @@ public:
/// marked as implicitly reading the 'CL' register, which it always does.
///
/// This method returns null if the instruction has no implicit uses.
const uint16_t *getImplicitUses() const { return ImplicitUses; }
const MCPhysReg *getImplicitUses() const { return ImplicitUses; }
/// \brief Return the number of implicit uses this instruction has.
unsigned getNumImplicitUses() const {
@ -494,7 +494,7 @@ public:
/// EAX/EDX/EFLAGS registers.
///
/// This method returns null if the instruction has no implicit defs.
const uint16_t *getImplicitDefs() const { return ImplicitDefs; }
const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; }
/// \brief Return the number of implicit defs this instruct has.
unsigned getNumImplicitDefs() const {
@ -509,7 +509,7 @@ public:
/// \brief Return true if this instruction implicitly
/// uses the specified physical register.
bool hasImplicitUseOfPhysReg(unsigned Reg) const {
if (const uint16_t *ImpUses = ImplicitUses)
if (const MCPhysReg *ImpUses = ImplicitUses)
for (; *ImpUses; ++ImpUses)
if (*ImpUses == Reg)
return true;

4
lib/CodeGen/MIRParser/MIParser.cpp
View File

@ -745,11 +745,11 @@ bool MIParser::verifyImplicitOperands(ArrayRef<ParsedMachineOperand> Operands,
// Gather all the expected implicit operands.
SmallVector<MachineOperand, 4> ImplicitOperands;
if (MCID.ImplicitDefs)
for (const uint16_t *ImpDefs = MCID.getImplicitDefs(); *ImpDefs; ++ImpDefs)
for (const MCPhysReg *ImpDefs = MCID.getImplicitDefs(); *ImpDefs; ++ImpDefs)
ImplicitOperands.push_back(
MachineOperand::CreateReg(*ImpDefs, true, true));
if (MCID.ImplicitUses)
for (const uint16_t *ImpUses = MCID.getImplicitUses(); *ImpUses; ++ImpUses)
for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses; ++ImpUses)
ImplicitOperands.push_back(
MachineOperand::CreateReg(*ImpUses, false, true));

6
lib/CodeGen/MachineInstr.cpp
View File

@ -631,10 +631,12 @@ void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
if (MCID->ImplicitDefs)
for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
++ImpDefs)
addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
if (MCID->ImplicitUses)
for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
++ImpUses)
addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
}

4
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
View File

@ -440,7 +440,7 @@ static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
NumRes = MCID.getNumDefs();
for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
if (Reg == *ImpDef)
break;
++NumRes;
@ -519,7 +519,7 @@ bool ScheduleDAGFast::DelayForLiveRegsBottomUp(SUnit *SU,
const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
if (!MCID.ImplicitDefs)
continue;
for (const uint16_t *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) {
for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) {
CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);
}
}

12
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
View File

@ -1206,7 +1206,7 @@ static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
NumRes = MCID.getNumDefs();
for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
if (Reg == *ImpDef)
break;
++NumRes;
@ -1335,7 +1335,7 @@ DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) {
const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
if (!MCID.ImplicitDefs)
continue;
for (const uint16_t *Reg = MCID.getImplicitDefs(); *Reg; ++Reg)
for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg)
CheckForLiveRegDef(SU, *Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
}
@ -2720,7 +2720,7 @@ static bool canClobberReachingPhysRegUse(const SUnit *DepSU, const SUnit *SU,
ScheduleDAGRRList *scheduleDAG,
const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI) {
const uint16_t *ImpDefs
const MCPhysReg *ImpDefs
= TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs();
const uint32_t *RegMask = getNodeRegMask(SU->getNode());
if(!ImpDefs && !RegMask)
@ -2739,7 +2739,7 @@ static bool canClobberReachingPhysRegUse(const SUnit *DepSU, const SUnit *SU,
return true;
if (ImpDefs)
for (const uint16_t *ImpDef = ImpDefs; *ImpDef; ++ImpDef)
for (const MCPhysReg *ImpDef = ImpDefs; *ImpDef; ++ImpDef)
// Return true if SU clobbers this physical register use and the
// definition of the register reaches from DepSU. IsReachable queries
// a topological forward sort of the DAG (following the successors).
@ -2758,13 +2758,13 @@ static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU,
const TargetRegisterInfo *TRI) {
SDNode *N = SuccSU->getNode();
unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
const uint16_t *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs();
const MCPhysReg *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs();
assert(ImpDefs && "Caller should check hasPhysRegDefs");
for (const SDNode *SUNode = SU->getNode(); SUNode;
SUNode = SUNode->getGluedNode()) {
if (!SUNode->isMachineOpcode())
continue;
const uint16_t *SUImpDefs =
const MCPhysReg *SUImpDefs =
TII->get(SUNode->getMachineOpcode()).getImplicitDefs();
const uint32_t *SURegMask = getNodeRegMask(SUNode);
if (!SUImpDefs && !SURegMask)

2
lib/MC/MCInstrDesc.cpp
View File

@ -53,7 +53,7 @@ bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI,
bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg,
const MCRegisterInfo *MRI) const {
if (const uint16_t *ImpDefs = ImplicitDefs)
if (const MCPhysReg *ImpDefs = ImplicitDefs)
for (; *ImpDefs; ++ImpDefs)
if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
return true;

4
lib/MC/MCParser/AsmParser.cpp
View File

@ -4753,8 +4753,8 @@ bool AsmParser::parseMSInlineAsm(
}
// Consider implicit defs to be clobbers. Think of cpuid and push.
ArrayRef<uint16_t> ImpDefs(Desc.getImplicitDefs(),
Desc.getNumImplicitDefs());
ArrayRef<MCPhysReg> ImpDefs(Desc.getImplicitDefs(),
Desc.getNumImplicitDefs());
ClobberRegs.insert(ClobberRegs.end(), ImpDefs.begin(), ImpDefs.end());
}

32
lib/Target/AArch64/AArch64CallingConvention.h
View File

@ -25,21 +25,21 @@
namespace {
using namespace llvm;
static const uint16_t XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
AArch64::X3, AArch64::X4, AArch64::X5,
AArch64::X6, AArch64::X7};
static const uint16_t HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
AArch64::H3, AArch64::H4, AArch64::H5,
AArch64::H6, AArch64::H7};
static const uint16_t SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
AArch64::S3, AArch64::S4, AArch64::S5,
AArch64::S6, AArch64::S7};
static const uint16_t DRegList[] = {AArch64::D0, AArch64::D1, AArch64::D2,
AArch64::D3, AArch64::D4, AArch64::D5,
AArch64::D6, AArch64::D7};
static const uint16_t QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
AArch64::Q3, AArch64::Q4, AArch64::Q5,
AArch64::Q6, AArch64::Q7};
static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
AArch64::X3, AArch64::X4, AArch64::X5,
AArch64::X6, AArch64::X7};
static const MCPhysReg HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
AArch64::H3, AArch64::H4, AArch64::H5,
AArch64::H6, AArch64::H7};
static const MCPhysReg SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
AArch64::S3, AArch64::S4, AArch64::S5,
AArch64::S6, AArch64::S7};
static const MCPhysReg DRegList[] = {AArch64::D0, AArch64::D1, AArch64::D2,
AArch64::D3, AArch64::D4, AArch64::D5,
AArch64::D6, AArch64::D7};
static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
AArch64::Q3, AArch64::Q4, AArch64::Q5,
AArch64::Q6, AArch64::Q7};
static bool finishStackBlock(SmallVectorImpl<CCValAssign> &PendingMembers,
MVT LocVT, ISD::ArgFlagsTy &ArgFlags,
@ -86,7 +86,7 @@ static bool CC_AArch64_Custom_Block(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
ISD::ArgFlagsTy &ArgFlags, CCState &State) {
// Try to allocate a contiguous block of registers, each of the correct
// size to hold one member.
ArrayRef<uint16_t> RegList;
ArrayRef<MCPhysReg> RegList;
if (LocVT.SimpleTy == MVT::i64)
RegList = XRegList;
else if (LocVT.SimpleTy == MVT::f16)

18
lib/Target/ARM/ARMCallingConv.h
View File

@ -160,15 +160,15 @@ static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
State);
}
static const uint16_t RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
static const uint16_t SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
ARM::S4, ARM::S5, ARM::S6, ARM::S7,
ARM::S8, ARM::S9, ARM::S10, ARM::S11,
ARM::S12, ARM::S13, ARM::S14, ARM::S15 };
static const uint16_t DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
static const uint16_t QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 };
static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
ARM::S4, ARM::S5, ARM::S6, ARM::S7,
ARM::S8, ARM::S9, ARM::S10, ARM::S11,
ARM::S12, ARM::S13, ARM::S14, ARM::S15 };
static const MCPhysReg DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
static const MCPhysReg QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 };
// Allocate part of an AAPCS HFA or HVA. We assume that each member of the HA
@ -203,7 +203,7 @@ static bool CC_ARM_AAPCS_Custom_Aggregate(unsigned &ValNo, MVT &ValVT,
unsigned StackAlign = DL.getStackAlignment();
unsigned Align = std::min(PendingMembers[0].getExtraInfo(), StackAlign);
ArrayRef<uint16_t> RegList;
ArrayRef<MCPhysReg> RegList;
switch (LocVT.SimpleTy) {
case MVT::i32: {
RegList = RRegList;

2
lib/Target/ARM/ARMFastISel.cpp
View File

@ -3036,7 +3036,7 @@ bool ARMFastISel::fastLowerArguments() {
}
static const uint16_t GPRArgRegs[] = {
static const MCPhysReg GPRArgRegs[] = {
ARM::R0, ARM::R1, ARM::R2, ARM::R3
};

2
lib/Target/ARM/Thumb2SizeReduction.cpp
View File

@ -218,7 +218,7 @@ Thumb2SizeReduce::Thumb2SizeReduce(std::function<bool(const Function &)> Ftor)
}
static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) {
for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
for (const MCPhysReg *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
if (*Regs == ARM::CPSR)
return true;
return false;

32
lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
View File

@ -471,7 +471,7 @@ extern const MCInstrDesc HexagonInsts[];
}
static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
ArrayRef<uint16_t> Table) {
ArrayRef<MCPhysReg> Table) {
if (RegNo < Table.size()) {
Inst.addOperand(MCOperand::createReg(Table[RegNo]));
return MCDisassembler::Success;
@ -489,7 +489,7 @@ static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder) {
static const uint16_t IntRegDecoderTable[] = {
static const MCPhysReg IntRegDecoderTable[] = {
Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
@ -498,13 +498,13 @@ static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
Hexagon::R30, Hexagon::R31};
return (DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable));
return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable);
}
static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/,
const void *Decoder) {
static const uint16_t VecRegDecoderTable[] = {
static const MCPhysReg VecRegDecoderTable[] = {
Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
@ -513,25 +513,25 @@ static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo,
Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
Hexagon::V30, Hexagon::V31};
return (DecodeRegisterClass(Inst, RegNo, VecRegDecoderTable));
return DecodeRegisterClass(Inst, RegNo, VecRegDecoderTable);
}
static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/,
const void *Decoder) {
static const uint16_t DoubleRegDecoderTable[] = {
static const MCPhysReg DoubleRegDecoderTable[] = {
Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
return (DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable));
return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable);
}
static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/,
const void *Decoder) {
static const uint16_t VecDblRegDecoderTable[] = {
static const MCPhysReg VecDblRegDecoderTable[] = {
Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3,
Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7,
Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11,
@ -543,25 +543,25 @@ static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo,
static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/,
const void *Decoder) {
static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
Hexagon::P2, Hexagon::P3};
static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
Hexagon::P2, Hexagon::P3};
return (DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable));
return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable);
}
static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/,
const void *Decoder) {
static const uint16_t VecPredRegDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
Hexagon::Q2, Hexagon::Q3};
static const MCPhysReg VecPredRegDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
Hexagon::Q2, Hexagon::Q3};
return (DecodeRegisterClass(Inst, RegNo, VecPredRegDecoderTable));
return DecodeRegisterClass(Inst, RegNo, VecPredRegDecoderTable);
}
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/,
const void *Decoder) {
static const uint16_t CtrlRegDecoderTable[] = {
static const MCPhysReg CtrlRegDecoderTable[] = {
Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1,
Hexagon::P3_0, Hexagon::C5, Hexagon::C6, Hexagon::C7,
Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP,
@ -582,7 +582,7 @@ static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/,
const void *Decoder) {
static const uint16_t CtrlReg64DecoderTable[] = {
static const MCPhysReg CtrlReg64DecoderTable[] = {
Hexagon::C1_0, Hexagon::NoRegister,
Hexagon::C3_2, Hexagon::NoRegister,
Hexagon::C7_6, Hexagon::NoRegister,

4
lib/Target/Hexagon/HexagonGenMux.cpp
View File

@ -120,10 +120,10 @@ void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs,
// First, get the implicit defs and uses for this instruction.
unsigned Opc = MI->getOpcode();
const MCInstrDesc &D = HII->get(Opc);
if (const uint16_t *R = D.ImplicitDefs)
if (const MCPhysReg *R = D.ImplicitDefs)
while (*R)
expandReg(*R++, Defs);
if (const uint16_t *R = D.ImplicitUses)
if (const MCPhysReg *R = D.ImplicitUses)
while (*R)
expandReg(*R++, Uses);

24
lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -316,18 +316,18 @@ static bool CC_HexagonVector(unsigned ValNo, MVT ValVT,
MVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State) {
static const uint16_t VecLstS[] = { Hexagon::V0, Hexagon::V1,
Hexagon::V2, Hexagon::V3,
Hexagon::V4, Hexagon::V5,
Hexagon::V6, Hexagon::V7,
Hexagon::V8, Hexagon::V9,
Hexagon::V10, Hexagon::V11,
Hexagon::V12, Hexagon::V13,
Hexagon::V14, Hexagon::V15};
static const uint16_t VecLstD[] = { Hexagon::W0, Hexagon::W1,
Hexagon::W2, Hexagon::W3,
Hexagon::W4, Hexagon::W5,
Hexagon::W6, Hexagon::W7};
static const MCPhysReg VecLstS[] = { Hexagon::V0, Hexagon::V1,
Hexagon::V2, Hexagon::V3,
Hexagon::V4, Hexagon::V5,
Hexagon::V6, Hexagon::V7,
Hexagon::V8, Hexagon::V9,
Hexagon::V10, Hexagon::V11,
Hexagon::V12, Hexagon::V13,
Hexagon::V14, Hexagon::V15};
static const MCPhysReg VecLstD[] = { Hexagon::W0, Hexagon::W1,
Hexagon::W2, Hexagon::W3,
Hexagon::W4, Hexagon::W5,
Hexagon::W6, Hexagon::W7};
auto &MF = State.getMachineFunction();
auto &HST = MF.getSubtarget<HexagonSubtarget>();
bool UseHVX = HST.useHVXOps();

2
lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
View File

@ -85,7 +85,7 @@ void HexagonMCChecker::init(MCInst const& MCI) {
}
// Get implicit register definitions.
const uint16_t* ImpDefs = MCID.getImplicitDefs();
const MCPhysReg *ImpDefs = MCID.getImplicitDefs();
for (unsigned i = 0; i < MCID.getNumImplicitDefs(); ++i) {
unsigned R = ImpDefs[i];

2
lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
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@ -334,7 +334,7 @@ static Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI,
// The only relocs left should be GP relative:
default:
if (MCID.mayStore() || MCID.mayLoad()) {
for (const uint16_t *ImpUses = MCID.getImplicitUses(); *ImpUses;
for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses;
++ImpUses) {
if (*ImpUses == Hexagon::GP) {
switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) {

2
lib/Target/PowerPC/PPCFrameLowering.cpp
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@ -30,7 +30,7 @@ using namespace llvm;
/// VRRegNo - Map from a numbered VR register to its enum value.
///
static const uint16_t VRRegNo[] = {
static const MCPhysReg VRRegNo[] = {
PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,

4
lib/Target/PowerPC/PPCInstrInfo.cpp
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@ -1748,13 +1748,13 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr,
MI->setDesc(NewDesc);
if (NewDesc.ImplicitDefs)
for (const uint16_t *ImpDefs = NewDesc.getImplicitDefs();
for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
*ImpDefs; ++ImpDefs)
if (!MI->definesRegister(*ImpDefs))
MI->addOperand(*MI->getParent()->getParent(),
MachineOperand::CreateReg(*ImpDefs, true, true));
if (NewDesc.ImplicitUses)
for (const uint16_t *ImpUses = NewDesc.getImplicitUses();
for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
*ImpUses; ++ImpUses)
if (!MI->readsRegister(*ImpUses))
MI->addOperand(*MI->getParent()->getParent(),

6
lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
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@ -639,13 +639,13 @@ private:
/// \brief Get the compact unwind number for a given register. The number
/// corresponds to the enum lists in compact_unwind_encoding.h.
int getCompactUnwindRegNum(unsigned Reg) const {
static const uint16_t CU32BitRegs[7] = {
static const MCPhysReg CU32BitRegs[7] = {
X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
};
static const uint16_t CU64BitRegs[] = {
static const MCPhysReg CU64BitRegs[] = {
X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
};
const uint16_t *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
const MCPhysReg *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
for (int Idx = 1; *CURegs; ++CURegs, ++Idx)
if (*CURegs == Reg)
return Idx;

2
utils/TableGen/InstrInfoEmitter.cpp
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@ -74,7 +74,7 @@ private:
static void PrintDefList(const std::vector<Record*> &Uses,
unsigned Num, raw_ostream &OS) {
OS << "static const uint16_t ImplicitList" << Num << "[] = { ";
OS << "static const MCPhysReg ImplicitList" << Num << "[] = { ";
for (unsigned i = 0, e = Uses.size(); i != e; ++i)
OS << getQualifiedName(Uses[i]) << ", ";
OS << "0 };\n";