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Fix coalescing with IMPLICIT_DEF values.
PHIElimination inserts IMPLICIT_DEF instructions to guarantee that all PHI predecessors have a live-out value. These IMPLICIT_DEF values are not considered to be real interference when coalescing virtual registers: %vreg1 = IMPLICIT_DEF %vreg2 = MOV32r0 When joining %vreg1 and %vreg2, the IMPLICIT_DEF instruction and its value number should simply be erased since the %vreg2 value number now provides a live-out value for the PHI predecesor block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165813 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
5628920346
commit
795f951c6d
@ -1241,6 +1241,9 @@ class JoinVals {
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// Value in the other live range that overlaps this def, if any.
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VNInfo *OtherVNI;
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// Is this value an IMPLICIT_DEF?
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bool IsImplicitDef;
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// True when the live range of this value will be pruned because of an
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// overlapping CR_Replace value in the other live range.
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bool Pruned;
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@ -1249,7 +1252,8 @@ class JoinVals {
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bool PrunedComputed;
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Val() : Resolution(CR_Keep), WriteLanes(0), ValidLanes(0),
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RedefVNI(0), OtherVNI(0), Pruned(false), PrunedComputed(false) {}
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RedefVNI(0), OtherVNI(0), IsImplicitDef(false), Pruned(false),
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PrunedComputed(false) {}
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bool isAnalyzed() const { return WriteLanes != 0; }
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};
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@ -1385,8 +1389,10 @@ JoinVals::analyzeValue(unsigned ValNo, JoinVals &Other) {
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}
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// An IMPLICIT_DEF writes undef values.
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if (DefMI->isImplicitDef())
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if (DefMI->isImplicitDef()) {
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V.IsImplicitDef = true;
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V.ValidLanes &= ~V.WriteLanes;
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}
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}
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// Find the value in Other that overlaps VNI->def, if any.
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@ -1724,22 +1730,29 @@ void JoinVals::pruneValues(JoinVals &Other,
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switch (Vals[i].Resolution) {
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case CR_Keep:
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break;
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case CR_Replace:
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case CR_Replace: {
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// This value takes precedence over the value in Other.LI.
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LIS->pruneValue(&Other.LI, Def, &EndPoints);
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// Remove <def,read-undef> flags. This def is now a partial redef.
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if (!Def.isBlock()) {
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// Check if we're replacing an IMPLICIT_DEF value. The IMPLICIT_DEF
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// instructions are only inserted to provide a live-out value for PHI
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// predecessors, so the instruction should simply go away once its value
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// has been replaced.
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Val &OtherV = Other.Vals[Vals[i].OtherVNI->id];
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bool EraseImpDef = OtherV.IsImplicitDef && OtherV.Resolution == CR_Keep;
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if (!EraseImpDef && !Def.isBlock()) {
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// Remove <def,read-undef> flags. This def is now a partial redef.
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for (MIOperands MO(Indexes->getInstructionFromIndex(Def));
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MO.isValid(); ++MO)
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if (MO->isReg() && MO->isDef() && MO->getReg() == LI.reg)
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MO->setIsUndef(false);
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// This value will reach instructions below, but we need to make sure
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// the live range also reaches the instruction at Def.
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EndPoints.push_back(Def);
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// This value will reach instructions below, but we need to make sure
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// the live range also reaches the instruction at Def.
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EndPoints.push_back(Def);
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}
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DEBUG(dbgs() << "\t\tpruned " << PrintReg(Other.LI.reg) << " at " << Def
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<< ": " << Other.LI << '\n');
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break;
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}
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case CR_Erase:
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case CR_Merge:
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if (isPrunedValue(i, Other)) {
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@ -1762,21 +1775,41 @@ void JoinVals::pruneValues(JoinVals &Other,
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void JoinVals::eraseInstrs(SmallPtrSet<MachineInstr*, 8> &ErasedInstrs,
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SmallVectorImpl<unsigned> &ShrinkRegs) {
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for (unsigned i = 0, e = LI.getNumValNums(); i != e; ++i) {
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if (Vals[i].Resolution != CR_Erase)
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continue;
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// Get the def location before markUnused() below invalidates it.
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SlotIndex Def = LI.getValNumInfo(i)->def;
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MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
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assert(MI && "No instruction to erase");
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if (MI->isCopy()) {
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unsigned Reg = MI->getOperand(1).getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg) &&
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Reg != CP.getSrcReg() && Reg != CP.getDstReg())
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ShrinkRegs.push_back(Reg);
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switch (Vals[i].Resolution) {
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case CR_Keep:
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// If an IMPLICIT_DEF value is pruned, it doesn't serve a purpose any
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// longer. The IMPLICIT_DEF instructions are only inserted by
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// PHIElimination to guarantee that all PHI predecessors have a value.
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if (!Vals[i].IsImplicitDef || !Vals[i].Pruned)
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break;
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// Remove value number i from LI. Note that this VNInfo is still present
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// in NewVNInfo, so it will appear as an unused value number in the final
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// joined interval.
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LI.getValNumInfo(i)->markUnused();
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LI.removeValNo(LI.getValNumInfo(i));
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DEBUG(dbgs() << "\t\tremoved " << i << '@' << Def << ": " << LI << '\n');
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// FALL THROUGH.
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case CR_Erase: {
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MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
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assert(MI && "No instruction to erase");
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if (MI->isCopy()) {
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unsigned Reg = MI->getOperand(1).getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg) &&
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Reg != CP.getSrcReg() && Reg != CP.getDstReg())
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ShrinkRegs.push_back(Reg);
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}
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ErasedInstrs.insert(MI);
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DEBUG(dbgs() << "\t\terased:\t" << Def << '\t' << *MI);
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LIS->RemoveMachineInstrFromMaps(MI);
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MI->eraseFromParent();
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break;
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}
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default:
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break;
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}
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ErasedInstrs.insert(MI);
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DEBUG(dbgs() << "\t\terased:\t" << Def << '\t' << *MI);
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LIS->RemoveMachineInstrFromMaps(MI);
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MI->eraseFromParent();
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}
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}
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@ -477,3 +477,106 @@ for.inc: ; preds = %for.cond
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}
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declare void @fn3(...)
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; Check coalescing of IMPLICIT_DEF instructions:
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;
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; %vreg1 = IMPLICIT_DEF
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; %vreg2 = MOV32r0
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;
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; When coalescing %vreg1 and %vreg2, the IMPLICIT_DEF instruction should be
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; erased along with its value number.
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;
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define void @rdar12474033() nounwind ssp {
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bb:
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br i1 undef, label %bb21, label %bb1
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bb1: ; preds = %bb
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switch i32 undef, label %bb10 [
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i32 4, label %bb2
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i32 1, label %bb9
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i32 5, label %bb3
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i32 6, label %bb3
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i32 2, label %bb9
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]
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bb2: ; preds = %bb1
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unreachable
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bb3: ; preds = %bb1, %bb1
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br i1 undef, label %bb4, label %bb5
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bb4: ; preds = %bb3
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unreachable
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bb5: ; preds = %bb3
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%tmp = load <4 x float>* undef, align 1
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%tmp6 = bitcast <4 x float> %tmp to i128
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%tmp7 = load <4 x float>* undef, align 1
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%tmp8 = bitcast <4 x float> %tmp7 to i128
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br label %bb10
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bb9: ; preds = %bb1, %bb1
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unreachable
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bb10: ; preds = %bb5, %bb1
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%tmp11 = phi i128 [ undef, %bb1 ], [ %tmp6, %bb5 ]
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%tmp12 = phi i128 [ 0, %bb1 ], [ %tmp8, %bb5 ]
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switch i32 undef, label %bb21 [
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i32 2, label %bb18
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i32 3, label %bb13
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i32 5, label %bb16
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i32 6, label %bb17
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i32 1, label %bb18
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]
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bb13: ; preds = %bb10
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br i1 undef, label %bb15, label %bb14
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bb14: ; preds = %bb13
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br label %bb21
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bb15: ; preds = %bb13
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unreachable
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bb16: ; preds = %bb10
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unreachable
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bb17: ; preds = %bb10
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unreachable
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bb18: ; preds = %bb10, %bb10
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%tmp19 = bitcast i128 %tmp11 to <4 x float>
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%tmp20 = bitcast i128 %tmp12 to <4 x float>
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br label %bb21
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bb21: ; preds = %bb18, %bb14, %bb10, %bb
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%tmp22 = phi <4 x float> [ undef, %bb ], [ undef, %bb10 ], [ undef, %bb14 ], [ %tmp20, %bb18 ]
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%tmp23 = phi <4 x float> [ undef, %bb ], [ undef, %bb10 ], [ undef, %bb14 ], [ %tmp19, %bb18 ]
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store <4 x float> %tmp23, <4 x float>* undef, align 16
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store <4 x float> %tmp22, <4 x float>* undef, align 16
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switch i32 undef, label %bb29 [
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i32 5, label %bb27
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i32 1, label %bb24
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i32 2, label %bb25
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i32 14, label %bb28
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i32 4, label %bb26
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]
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bb24: ; preds = %bb21
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unreachable
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bb25: ; preds = %bb21
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br label %bb29
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bb26: ; preds = %bb21
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br label %bb29
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bb27: ; preds = %bb21
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unreachable
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bb28: ; preds = %bb21
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br label %bb29
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bb29: ; preds = %bb28, %bb26, %bb25, %bb21
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unreachable
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}
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