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AArch64AsmParser: tablegen the isBranchTarget helper functions

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Use tablegen to autogenerate isBranchtarget helper functions. This is a cleanup
that removes almost identical functions that differ only in a few constants.

Differential Revision: https://reviews.llvm.org/D30160


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295649 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sjoerd Meijer 2017-02-20 10:57:54 +00:00
parent 5b71a58dbb
commit 7a9ab014fe
2 changed files with 18 additions and 37 deletions
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25
lib/Target/AArch64/AArch64InstrFormats.td
View File

@ -265,6 +265,20 @@ def Imm1_16Operand : AsmImmRange<1, 16>;
def Imm1_32Operand : AsmImmRange<1, 32>;
def Imm1_64Operand : AsmImmRange<1, 64>;
class BranchTarget<int N> : AsmOperandClass {
let Name = "BranchTarget" # N;
let DiagnosticType = "InvalidLabel";
let PredicateMethod = "isBranchTarget<" # N # ">";
}
class PCRelLabel<int N> : BranchTarget<N> {
let Name = "PCRelLabel" # N;
}
def BranchTarget14Operand : BranchTarget<14>;
def BranchTarget26Operand : BranchTarget<26>;
def PCRelLabel19Operand : PCRelLabel<19>;
def MovZSymbolG3AsmOperand : AsmOperandClass {
let Name = "MovZSymbolG3";
let RenderMethod = "addImmOperands";
@ -1096,10 +1110,6 @@ def inv_ccode : Operand<i32> {
// Conditional branch target. 19-bit immediate. The low two bits of the target
// offset are implied zero and so are not part of the immediate.
def PCRelLabel19Operand : AsmOperandClass {
let Name = "PCRelLabel19";
let DiagnosticType = "InvalidLabel";
}
def am_brcond : Operand<OtherVT> {
let EncoderMethod = "getCondBranchTargetOpValue";
let DecoderMethod = "DecodePCRelLabel19";
@ -1156,9 +1166,6 @@ multiclass CmpBranch<bit op, string asm, SDNode node> {
//---
// Test-and-branch target. 14-bit sign-extended immediate. The low two bits of
// the target offset are implied zero and so are not part of the immediate.
def BranchTarget14Operand : AsmOperandClass {
let Name = "BranchTarget14";
}
def am_tbrcond : Operand<OtherVT> {
let EncoderMethod = "getTestBranchTargetOpValue";
let PrintMethod = "printAlignedLabel";
@ -1235,10 +1242,6 @@ multiclass TestBranch<bit op, string asm, SDNode node> {
//---
// Unconditional branch (immediate) instructions.
//---
def BranchTarget26Operand : AsmOperandClass {
let Name = "BranchTarget26";
let DiagnosticType = "InvalidLabel";
}
def am_b_target : Operand<OtherVT> {
let EncoderMethod = "getBranchTargetOpValue";
let PrintMethod = "printAlignedLabel";

30
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
View File

@ -665,7 +665,8 @@ public:
return AArch64_AM::isAdvSIMDModImmType10(MCE->getValue());
}
bool isBranchTarget26() const {
template<int N>
bool isBranchTarget() const {
if (!isImm())
return false;
const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
@ -674,31 +675,8 @@ public:
int64_t Val = MCE->getValue();
if (Val & 0x3)
return false;
return (Val >= -(0x2000000 << 2) && Val <= (0x1ffffff << 2));
}
bool isPCRelLabel19() const {
if (!isImm())
return false;
const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
if (!MCE)
return true;
int64_t Val = MCE->getValue();
if (Val & 0x3)
return false;
return (Val >= -(0x40000 << 2) && Val <= (0x3ffff << 2));
}
bool isBranchTarget14() const {
if (!isImm())
return false;
const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
if (!MCE)
return true;
int64_t Val = MCE->getValue();
if (Val & 0x3)
return false;
return (Val >= -(0x2000 << 2) && Val <= (0x1fff << 2));
assert(N > 0 && "Branch target immediate cannot be 0 bits!");
return (Val >= -((1<<(N-1)) << 2) && Val <= (((1<<(N-1))-1) << 2));
}
bool