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Move MOVD/MODQ code around, creating sections for each of them
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107308 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
d540801e13
commit
7ac7ed868a
@ -2885,41 +2885,9 @@ def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
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} // ExeDomain = SSEPackedInt
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//===---------------------------------------------------------------------===//
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// SSE2 - Packed Misc Integer Instructions
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// SSE2 - Move Doubleword
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//===---------------------------------------------------------------------===//
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// Flush cache
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def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
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"clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
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TB, Requires<[HasSSE2]>;
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// Load, store, and memory fence
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def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
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"lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
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def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
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"mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
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// Pause. This "instruction" is encoded as "rep; nop", so even though it
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// was introduced with SSE2, it's backward compatible.
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def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
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//TODO: custom lower this so as to never even generate the noop
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def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
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(i8 0)), (NOOP)>;
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def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
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def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
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def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
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(i8 1)), (MFENCE)>;
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// Alias instructions that map zero vector to pxor / xorp* for sse.
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// We set canFoldAsLoad because this can be converted to a constant-pool
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// load of an all-ones value if folding it would be beneficial.
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let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
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isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
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// FIXME: Change encoding to pseudo.
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def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
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[(set VR128:$dst, (v4i32 immAllOnesV))]>;
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def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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@ -2937,20 +2905,6 @@ def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
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// SSE2 instructions with XS prefix
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def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
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"movq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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(v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
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Requires<[HasSSE2]>;
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def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
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"movq\t{$src, $dst|$dst, $src}",
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[(store (i64 (vector_extract (v2i64 VR128:$src),
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(iPTR 0))), addr:$dst)]>;
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def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
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(f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
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def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
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@ -2967,11 +2921,6 @@ def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
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// Store / copy lower 64-bits of a XMM register.
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def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
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"movq\t{$src, $dst|$dst, $src}",
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[(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
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// movd / movq to XMM register zero-extends
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let AddedComplexity = 15 in {
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def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
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@ -2998,7 +2947,32 @@ def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
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(MOVZDI2PDIrm addr:$src)>;
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def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
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(MOVZDI2PDIrm addr:$src)>;
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}
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//===---------------------------------------------------------------------===//
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// SSE2 - Move Quadword
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//===---------------------------------------------------------------------===//
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// SSE2 instructions with XS prefix
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def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
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"movq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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(v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
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Requires<[HasSSE2]>;
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def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
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"movq\t{$src, $dst|$dst, $src}",
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[(store (i64 (vector_extract (v2i64 VR128:$src),
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(iPTR 0))), addr:$dst)]>;
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def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
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(f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
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// Store / copy lower 64-bits of a XMM register.
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def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
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"movq\t{$src, $dst|$dst, $src}",
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[(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
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let AddedComplexity = 20 in {
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def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
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"movq\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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@ -3039,6 +3013,42 @@ def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
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def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"movq\t{$src, $dst|$dst, $src}", []>, XS;
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//===---------------------------------------------------------------------===//
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// SSE2 - Misc Instructions
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//===---------------------------------------------------------------------===//
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// Flush cache
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def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
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"clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
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TB, Requires<[HasSSE2]>;
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// Load, store, and memory fence
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def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
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"lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
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def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
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"mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
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// Pause. This "instruction" is encoded as "rep; nop", so even though it
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// was introduced with SSE2, it's backward compatible.
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def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
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//TODO: custom lower this so as to never even generate the noop
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def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
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(i8 0)), (NOOP)>;
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def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
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def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
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def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
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(i8 1)), (MFENCE)>;
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// Alias instructions that map zero vector to pxor / xorp* for sse.
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// We set canFoldAsLoad because this can be converted to a constant-pool
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// load of an all-ones value if folding it would be beneficial.
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let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
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isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
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// FIXME: Change encoding to pseudo.
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def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
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[(set VR128:$dst, (v4i32 immAllOnesV))]>;
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//===---------------------------------------------------------------------===//
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// SSE3 Instructions
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//===---------------------------------------------------------------------===//
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