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[Hexagon] Add intrinsics for masked vector stores

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Patch by Harsha Jagasia.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295879 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek 2017-02-22 21:23:09 +00:00
parent c1d17d5f71
commit 7af390a681
4 changed files with 146 additions and 0 deletions
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45
include/llvm/IR/IntrinsicsHexagon.td
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@ -5658,6 +5658,22 @@ class Hexagon_v2048v2048v1024v1024i_Intrinsic<string GCCIntSuffix>
[llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
[IntrNoMem]>;
//
// Hexagon_vv64ivmemv512_Intrinsic<string GCCIntSuffix>
// tag: V6_vS32b_qpred_ai
class Hexagon_vv64ivmemv512_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[], [llvm_v512i1_ty,llvm_ptr_ty,llvm_v16i32_ty],
[IntrArgMemOnly]>;
//
// Hexagon_vv128ivmemv1024_Intrinsic<string GCCIntSuffix>
// tag: V6_vS32b_qpred_ai_128B
class Hexagon_vv128ivmemv1024_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[], [llvm_v1024i1_ty,llvm_ptr_ty,llvm_v32i32_ty],
[IntrArgMemOnly]>;
//
// BUILTIN_INFO(HEXAGON.S6_rol_i_r,SI_ftype_SISI,2)
// tag : S6_rol_i_r
@ -9326,6 +9342,34 @@ Hexagon_v1024v1024v512v512i_Intrinsic<"HEXAGON_V6_vlutvwh_oracc">;
def int_hexagon_V6_vlutvwh_oracc_128B :
Hexagon_v2048v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvwh_oracc_128B">;
//
// Masked vector stores
//
def int_hexagon_V6_vmaskedstoreq :
Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstoreq">;
def int_hexagon_V6_vmaskedstorenq :
Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorenq">;
def int_hexagon_V6_vmaskedstorentq :
Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorentq">;
def int_hexagon_V6_vmaskedstorentnq :
Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorentnq">;
def int_hexagon_V6_vmaskedstoreq_128B :
Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstoreq_128B">;
def int_hexagon_V6_vmaskedstorenq_128B :
Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorenq_128B">;
def int_hexagon_V6_vmaskedstorentq_128B :
Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorentq_128B">;
def int_hexagon_V6_vmaskedstorentnq_128B :
Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorentnq_128B">;
///
/// HexagonV62 intrinsics
///
@ -9594,6 +9638,7 @@ class Hexagon_V62_v2048v2048v1024v1024i_Intrinsic<string GCCIntSuffix>
[llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
[IntrNoMem]>;
//
// BUILTIN_INFO(HEXAGON.M6_vabsdiffb,DI_ftype_DIDI,2)
// tag : M6_vabsdiffb

19
lib/Target/Hexagon/HexagonIntrinsics.td
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@ -1347,6 +1347,25 @@ def: T_stc_pat<S2_storeri_pci, int_hexagon_circ_stw, s4_2ImmPred, I32>;
def: T_stc_pat<S2_storerd_pci, int_hexagon_circ_std, s4_3ImmPred, I64>;
def: T_stc_pat<S2_storerf_pci, int_hexagon_circ_sthhi, s4_1ImmPred, I32>;
multiclass MaskedStore <InstHexagon MI, Intrinsic IntID> {
def : Pat<(IntID VecPredRegs:$src1, IntRegs:$src2, VectorRegs:$src3),
(MI VecPredRegs:$src1, IntRegs:$src2, #0, VectorRegs:$src3)>,
Requires<[UseHVXSgl]>;
def : Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
IntRegs:$src2,
VectorRegs128B:$src3),
(!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1,
IntRegs:$src2, #0,
VectorRegs128B:$src3)>,
Requires<[UseHVXDbl]>;
}
defm : MaskedStore <V6_vS32b_qpred_ai, int_hexagon_V6_vmaskedstoreq>;
defm : MaskedStore <V6_vS32b_nqpred_ai, int_hexagon_V6_vmaskedstorenq>;
defm : MaskedStore <V6_vS32b_nt_qpred_ai, int_hexagon_V6_vmaskedstorentq>;
defm : MaskedStore <V6_vS32b_nt_nqpred_ai, int_hexagon_V6_vmaskedstorentnq>;
include "HexagonIntrinsicsV3.td"
include "HexagonIntrinsicsV4.td"
include "HexagonIntrinsicsV5.td"

41
test/CodeGen/Hexagon/intrinsics/byte-store-double.ll Normal file
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@ -0,0 +1,41 @@
; RUN: llc -mattr=+hvx-double -march=hexagon -O2 < %s | FileCheck %s
; CHECK-LABEL: V6_vmaskedstoreq_128B
; CHECK: if (q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}}
; CHECK-LABEL: V6_vmaskedstorenq_128B
; CHECK: if (!q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}}
; CHECK-LABEL: V6_vmaskedstorentq_128B
; CHECK: if (q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0):nt = v{{[0-9]+}}
; CHECK-LABEL: V6_vmaskedstorentnq_128B
; CHECK: if (!q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0):nt = v{{[0-9]+}}
declare void @llvm.hexagon.V6.vmaskedstoreq.128B(<1024 x i1>, i8*, <32 x i32>)
define void @V6_vmaskedstoreq_128B( <32 x i32> %a, i8* %b, <32 x i32> %c) {
%1 = bitcast <32 x i32> %a to <1024 x i1>
call void @llvm.hexagon.V6.vmaskedstoreq.128B(<1024 x i1> %1, i8* %b, <32 x i32> %c)
ret void
}
declare void @llvm.hexagon.V6.vmaskedstorenq.128B(<1024 x i1>, i8*, <32 x i32>)
define void @V6_vmaskedstorenq_128B( <32 x i32> %a, i8* %b, <32 x i32> %c) {
%1 = bitcast <32 x i32> %a to <1024 x i1>
call void @llvm.hexagon.V6.vmaskedstorenq.128B(<1024 x i1> %1, i8* %b, <32 x i32> %c)
ret void
}
declare void @llvm.hexagon.V6.vmaskedstorentq.128B(<1024 x i1>, i8*, <32 x i32>)
define void @V6_vmaskedstorentq_128B( <32 x i32> %a, i8* %b, <32 x i32> %c) {
%1 = bitcast <32 x i32> %a to <1024 x i1>
call void @llvm.hexagon.V6.vmaskedstorentq.128B(<1024 x i1> %1, i8* %b, <32 x i32> %c)
ret void
}
declare void @llvm.hexagon.V6.vmaskedstorentnq.128B(<1024 x i1>, i8*, <32 x i32>)
define void @V6_vmaskedstorentnq_128B( <32 x i32> %a, i8* %b, <32 x i32> %c) {
%1 = bitcast <32 x i32> %a to <1024 x i1>
call void @llvm.hexagon.V6.vmaskedstorentnq.128B(<1024 x i1> %1, i8* %b, <32 x i32> %c)
ret void
}

41
test/CodeGen/Hexagon/intrinsics/byte-store.ll Normal file
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@ -0,0 +1,41 @@
; RUN: llc -mattr=+hvx -march=hexagon -O2 < %s | FileCheck %s
; CHECK-LABEL: V6_vmaskedstoreq
; CHECK: if (q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}}
; CHECK-LABEL: V6_vmaskedstorenq
; CHECK: if (!q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}}
; CHECK-LABEL: V6_vmaskedstorentq
; CHECK: if (q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0):nt = v{{[0-9]+}}
; CHECK-LABEL: V6_vmaskedstorentnq
; CHECK: if (!q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0):nt = v{{[0-9]+}}
declare void @llvm.hexagon.V6.vmaskedstoreq(<512 x i1>, i8*, <16 x i32>)
define void @V6_vmaskedstoreq( <16 x i32> %a, i8* %b, <16 x i32> %c) {
%1 = bitcast <16 x i32> %a to <512 x i1>
call void @llvm.hexagon.V6.vmaskedstoreq(<512 x i1> %1, i8* %b, <16 x i32> %c)
ret void
}
declare void @llvm.hexagon.V6.vmaskedstorenq(<512 x i1>, i8*, <16 x i32>)
define void @V6_vmaskedstorenq( <16 x i32> %a, i8* %b, <16 x i32> %c) {
%1 = bitcast <16 x i32> %a to <512 x i1>
call void @llvm.hexagon.V6.vmaskedstorenq(<512 x i1> %1, i8* %b, <16 x i32> %c)
ret void
}
declare void @llvm.hexagon.V6.vmaskedstorentq(<512 x i1>, i8*, <16 x i32>)
define void @V6_vmaskedstorentq( <16 x i32> %a, i8* %b, <16 x i32> %c) {
%1 = bitcast <16 x i32> %a to <512 x i1>
call void @llvm.hexagon.V6.vmaskedstorentq(<512 x i1> %1, i8* %b, <16 x i32> %c)
ret void
}
declare void @llvm.hexagon.V6.vmaskedstorentnq(<512 x i1>, i8*, <16 x i32>)
define void @V6_vmaskedstorentnq( <16 x i32> %a, i8* %b, <16 x i32> %c) {
%1 = bitcast <16 x i32> %a to <512 x i1>
call void @llvm.hexagon.V6.vmaskedstorentnq(<512 x i1> %1, i8* %b, <16 x i32> %c)
ret void
}