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Slightly change TableGen's definition of a register subclass.

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A subclass is allowed to have a larger spill size than the superclass, and the
spill alignment must be a multiple of the superclass alignment. This causes
the following new subclass relations:

=== Alpha ===
F4RC -> F8RC

=== PPC ===
F4RC -> F8RC

=== SPU ===
R8C -> R16C -> R32C/R32FP -> R64C/R64FP -> GPRC/VECREG

=== X86 ===
FR32  -> FR64  -> VR128
RFP32 -> RFP64 -> RFP80

These subclass relations are consistent with the behaviour of -join-cross-class-copies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70511 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2009-04-30 21:22:44 +00:00
parent 3d739fe375
commit 7afcc6aa27
1 changed files with 14 additions and 1 deletions
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15
utils/TableGen/RegisterInfoEmitter.cpp
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@ -340,8 +340,21 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
bool Empty = true;
for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
// RC2 is a sub-class of RC if it is a valid replacement for any
// instruction operand where an RC register is required. It must satisfy
// these conditions:
//
// 1. All RC2 registers are also in RC.
// 2. The RC2 spill size must not be smaller that the RC spill size.
// 3. RC2 spill alignment must be compatible with RC.
//
// Sub-classes are used to determine if a virtual register can be used
// as an instruction operand, or if it must be copied first.
if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() ||
RC.SpillSize != RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
(RC.SpillAlignment && RC2.SpillAlignment % RC.SpillAlignment) ||
RC.SpillSize > RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
continue;
if (!Empty) OS << ", ";