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[mips] Implement l[wd]c3, and s[wd]c3.
Summary: These instructions were added in MIPS-I, and MIPS-II but were removed in MIPS-III. Interestingly, GAS continues to accept them when assembling for MIPS-III. For the moment, these instructions will follow GAS and accept them for MIPS-III and newer but this will be tightened up when the invalid-*.s tests are added. Depends on D3647 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3648 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208311 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
parent
9f0141da2c
commit
7bd400ebfd
@ -272,11 +272,12 @@ public:
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/// context).
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RegKind_CCR = 128, /// CCR
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RegKind_HWRegs = 256, /// HWRegs
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RegKind_COP3 = 512, /// COP3
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/// Potentially any (e.g. $1)
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RegKind_Numeric = RegKind_GPR | RegKind_FGR | RegKind_FCC | RegKind_MSA128 |
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RegKind_MSACtrl | RegKind_COP2 | RegKind_ACC |
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RegKind_CCR | RegKind_HWRegs
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RegKind_CCR | RegKind_HWRegs | RegKind_COP3
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};
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private:
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@ -428,6 +429,14 @@ private:
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return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
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}
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/// Coerce the register to COP3 and return the real register for the
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/// current target.
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unsigned getCOP3Reg() const {
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assert(isRegIdx() && (RegIdx.Kind & RegKind_COP3) && "Invalid access!");
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unsigned ClassID = Mips::COP3RegClassID;
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return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
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}
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/// Coerce the register to ACC64DSP and return the real register for the
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/// current target.
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unsigned getACC64DSPReg() const {
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@ -539,6 +548,11 @@ public:
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Inst.addOperand(MCOperand::CreateReg(getCOP2Reg()));
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}
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void addCOP3AsmRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getCOP3Reg()));
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}
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void addACC64DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getACC64DSPReg()));
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@ -750,6 +764,9 @@ public:
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bool isCOP2AsmReg() const {
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return isRegIdx() && RegIdx.Kind & RegKind_COP2 && RegIdx.Index <= 31;
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}
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bool isCOP3AsmReg() const {
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return isRegIdx() && RegIdx.Kind & RegKind_COP3 && RegIdx.Index <= 31;
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}
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bool isMSA128AsmReg() const {
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return isRegIdx() && RegIdx.Kind & RegKind_MSA128 && RegIdx.Index <= 31;
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}
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@ -387,12 +387,22 @@ def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>,
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def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>,
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ISA_MIPS2, FGR_32;
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/// Cop2 Memory Instructions
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// Cop2 Memory Instructions
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// FIXME: These aren't really FPU instructions and as such don't belong in this
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// file
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def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>;
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def SWC2 : SW_FT<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>;
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def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>, ISA_MIPS2;
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def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>, ISA_MIPS2;
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// Cop3 Memory Instructions
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// FIXME: These aren't really FPU instructions and as such don't belong in this
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// file
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def LWC3 : LW_FT<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
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def SWC3 : SW_FT<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
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def LDC3 : LW_FT<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>, ISA_MIPS2;
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def SDC3 : SW_FT<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>, ISA_MIPS2;
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// Indexed loads and stores.
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// Base register + offset register addressing mode (indicated by "x" in the
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// instruction mnemonic) is disallowed under NaCl.
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@ -205,6 +205,10 @@ let Namespace = "Mips" in {
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foreach I = 0-31 in
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def COP2#I : MipsReg<#I, ""#I>;
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// COP3 registers.
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foreach I = 0-31 in
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def COP3#I : MipsReg<#I, ""#I>;
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// PC register
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def PC : Register<"pc">;
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@ -387,6 +391,10 @@ def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;
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def COP2 : RegisterClass<"Mips", [i32], 32, (sequence "COP2%u", 0, 31)>,
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Unallocatable;
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// Coprocessor 3 registers.
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def COP3 : RegisterClass<"Mips", [i32], 32, (sequence "COP3%u", 0, 31)>,
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Unallocatable;
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// Octeon multiplier and product registers
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def OCTEON_MPL : RegisterClass<"Mips", [i64], 64, (add MPL0, MPL1, MPL2)>,
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Unallocatable;
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@ -484,6 +492,10 @@ def COP2AsmOperand : MipsAsmRegOperand {
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let Name = "COP2AsmReg";
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}
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def COP3AsmOperand : MipsAsmRegOperand {
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let Name = "COP3AsmReg";
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}
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def HWRegsOpnd : RegisterOperand<HWRegs> {
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let ParserMatchClass = HWRegsAsmOperand;
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}
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@ -524,6 +536,10 @@ def COP2Opnd : RegisterOperand<COP2> {
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let ParserMatchClass = COP2AsmOperand;
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}
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def COP3Opnd : RegisterOperand<COP3> {
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let ParserMatchClass = COP3AsmOperand;
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}
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def MSA128BOpnd : RegisterOperand<MSA128B> {
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let ParserMatchClass = MSA128AsmOperand;
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}
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@ -8,7 +8,9 @@
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.set noat
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ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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ldc3 $29,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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sc $t7,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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sdc1 $f31,30574($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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sdc3 $12,5835($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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@ -4,7 +4,7 @@
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# RUN: 2>%t1
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# RUN: FileCheck %s < %t1
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.set noat
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.set noat
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ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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floor.w.d $f14,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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@ -8,5 +8,4 @@
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.set noat
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lwc0 c0_entrylo,-7321($s2)
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lwc3 $10,-32265($k0)
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swc0 c0_prid,18904($s3)
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@ -37,6 +37,7 @@
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lw $t0,5674($a1)
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lwc1 $f16,10225($k0)
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lwc2 $18,-841($a2)
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lwc3 $10,-32265($k0)
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lwl $s4,-4231($t7)
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lwr $zero,-19147($gp)
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mfc1 $a3,$f27
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@ -90,6 +91,7 @@
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sw $ra,-10160($sp)
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swc1 $f6,-8465($t8)
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swc2 $25,24880($s0)
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swc3 $10,-32265($k0)
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swl $t7,13694($s3)
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swr $s1,-26590($t6)
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tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
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@ -1,12 +0,0 @@
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# Instructions that should be valid but currently fail for known reasons (e.g.
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# they aren't implemented yet).
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# This test is set up to XPASS if any instruction generates an encoding.
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#
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# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 | not FileCheck %s
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# CHECK-NOT: encoding
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# XFAIL: *
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.set noat
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ldc3 $29,-28645($s1)
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lwc3 $10,-32265($k0)
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sdc3 $12,5835($t2)
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@ -36,6 +36,7 @@
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lbu $t0,30195($v1)
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ldc1 $f11,16391($s0)
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ldc2 $8,-21181($at)
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ldc3 $29,-28645($s1)
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lh $t3,-8556($s5)
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lhu $s3,-22851($v0)
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li $at,-29773
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@ -44,6 +45,7 @@
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lw $t0,5674($a1)
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lwc1 $f16,10225($k0)
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lwc2 $18,-841($a2)
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lwc3 $10,-32265($k0)
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lwl $s4,-4231($t7)
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lwr $zero,-19147($gp)
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mfc1 $a3,$f27
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@ -77,6 +79,7 @@
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sc $t7,18904($s3)
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sdc1 $f31,30574($t5)
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sdc2 $20,23157($s2)
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sdc3 $12,5835($t2)
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sh $t6,-6704($t7)
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sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
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sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
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@ -104,6 +107,7 @@
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sw $ra,-10160($sp)
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swc1 $f6,-8465($t8)
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swc2 $25,24880($s0)
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swc3 $10,-32265($k0)
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swl $t7,13694($s3)
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swr $s1,-26590($t6)
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teqi $s5,-17504
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@ -1,10 +0,0 @@
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# Instructions that should be valid but currently fail for known reasons (e.g.
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# they aren't implemented yet).
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# This test is set up to XPASS if any instruction generates an encoding.
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#
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# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips3 | not FileCheck %s
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# CHECK-NOT: encoding
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# XFAIL: *
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.set noat
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lwc3 $10,-32265($k0)
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@ -35,6 +35,4 @@
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c.ult.s $fcc7,$f24,$f10
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c.un.d $fcc6,$f23,$f24
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c.un.s $fcc1,$f30,$f4
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ldc3 $29,-28645($s1)
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rorv $t5,$a3,$s5
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sdc3 $12,5835($t2)
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@ -167,7 +167,6 @@
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lbe $t6,122($t1)
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lbue $t3,-108($t2)
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lbux $t1,$t6($v0)
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ldc3 $29,-28645($s1)
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lhe $s6,219($v1)
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lhue $gp,118($t3)
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lhx $sp,$k0($t7)
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@ -263,7 +262,6 @@
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rsqrt.s $f4,$f8
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sbe $s7,33($s1)
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sce $sp,189($t2)
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sdc3 $12,5835($t2)
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she $t8,105($v0)
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shilo $ac1,26
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shilov $ac2,$t2
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