RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-11-30 15:10:33 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Fix more of PR8825 by correctly using rGPR registers when lowering atomic

Browse Source 
compare-and-swap intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131518 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Cameron Zwarich 2011-05-18 02:20:07 +00:00
parent ef819d0ed8
commit 7d336c0c68
1 changed files with 11 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -4860,12 +4860,21 @@ ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
unsigned ptr = MI->getOperand(1).getReg();
unsigned oldval = MI->getOperand(2).getReg();
unsigned newval = MI->getOperand(3).getReg();
unsigned scratch = BB->getParent()->getRegInfo()
.createVirtualRegister(ARM::GPRRegisterClass);
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
DebugLoc dl = MI->getDebugLoc();
bool isThumb2 = Subtarget->isThumb2();
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
unsigned scratch =
MRI.createVirtualRegister(isThumb2 ? ARM::tGPRRegisterClass
: ARM::GPRRegisterClass);
if (isThumb2) {
MRI.constrainRegClass(dest, ARM::tGPRRegisterClass);
MRI.constrainRegClass(oldval, ARM::tGPRRegisterClass);
MRI.constrainRegClass(newval, ARM::tGPRRegisterClass);
}
unsigned ldrOpc, strOpc;
switch (Size) {
default: llvm_unreachable("unsupported size for AtomicCmpSwap!");