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Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.

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Added two test cases to arm-tests.txt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110880 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2010-08-11 23:35:12 +00:00
parent ebd53742c6
commit 7def14f40f
4 changed files with 12 additions and 9 deletions
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8
lib/Target/ARM/ARMInstrInfo.td
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@ -2356,7 +2356,7 @@ def MOVCCi : AI1<0b1101, (outs GPR:$dst),
// memory barriers protect the atomic sequences
let hasSideEffects = 1 in {
def DMBsy : AInoP<(outs), (ins), Pseudo, NoItinerary, "dmb", "",
def DMBsy : AInoP<(outs), (ins), MiscFrm, NoItinerary, "dmb", "",
[(ARMMemBarrier)]>, Requires<[IsARM, HasDB]> {
let Inst{31-4} = 0xf57ff05;
// FIXME: add support for options other than a full system DMB
@ -2364,7 +2364,7 @@ def DMBsy : AInoP<(outs), (ins), Pseudo, NoItinerary, "dmb", "",
let Inst{3-0} = 0b1111;
}
def DSBsy : AInoP<(outs), (ins), Pseudo, NoItinerary, "dsb", "",
def DSBsy : AInoP<(outs), (ins), MiscFrm, NoItinerary, "dsb", "",
[(ARMSyncBarrier)]>, Requires<[IsARM, HasDB]> {
let Inst{31-4} = 0xf57ff04;
// FIXME: add support for options other than a full system DSB
@ -2372,7 +2372,7 @@ def DSBsy : AInoP<(outs), (ins), Pseudo, NoItinerary, "dsb", "",
let Inst{3-0} = 0b1111;
}
def DMB_MCR : AInoP<(outs), (ins GPR:$zero), Pseudo, NoItinerary,
def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
"mcr", "\tp15, 0, $zero, c7, c10, 5",
[(ARMMemBarrierMCR GPR:$zero)]>,
Requires<[IsARM, HasV6]> {
@ -2380,7 +2380,7 @@ def DMB_MCR : AInoP<(outs), (ins GPR:$zero), Pseudo, NoItinerary,
// FIXME: add encoding
}
def DSB_MCR : AInoP<(outs), (ins GPR:$zero), Pseudo, NoItinerary,
def DSB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
"mcr", "\tp15, 0, $zero, c7, c10, 4",
[(ARMSyncBarrierMCR GPR:$zero)]>,
Requires<[IsARM, HasV6]> {

3
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -493,9 +493,6 @@ static inline ARM_AM::AMSubMode getAMSubModeForBits(unsigned bits) {
static bool DisassemblePseudo(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO) {
if (Opcode == ARM::DMBsy || Opcode == ARM::DSBsy)
return true;
assert(0 && "Unexpected pseudo instruction!");
return false;
}

4
lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
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@ -1629,8 +1629,8 @@ static inline bool t2MiscCtrlInstr(uint32_t insn) {
// A8.6.26
// t2BXJ -> Rn
//
// Miscellaneous control: t2Int_MemBarrierV7 (and its t2DMB variants),
// t2Int_SyncBarrierV7 (and its t2DSB varianst), t2ISBsy, t2CLREX
// Miscellaneous control: t2DMBsy (and its t2DMB variants),
// t2DSBsy (and its t2DSB varianst), t2ISBsy, t2CLREX
// -> no operand (except pred-imm pred-ccr for CLREX, memory barrier variants)
//
// Hint: t2NOP, t2YIELD, t2WFE, t2WFI, t2SEV

6
test/MC/Disassembler/arm-tests.txt
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@ -12,9 +12,15 @@
# CHECK: cmn r0, #1
0x01 0x00 0x70 0xe3
# CHECK: dmb
0x5f 0xf0 0x7f 0xf5
# CHECK: dmb nshst
0x56 0xf0 0x7f 0xf5
# CHECK: dsb
0x4f 0xf0 0x7f 0xf5
# CHECK: ldclvc p5, cr15, [r8], #-0
0x00 0xf5 0x78 0x7c