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new testcases for -enable-tail-merge default handling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37287 91177308-0d34-0410-b5e6-96231b3b80d8
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Dale Johannesen
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68
test/CodeGen/ARM/2007-05-22-tailmerge-3.ll
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68
test/CodeGen/ARM/2007-05-22-tailmerge-3.ll
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@ -0,0 +1,68 @@
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; RUN: llvm-as < %s | llc -march=arm | grep bl.*baz | wc -l | grep 1
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; RUN: llvm-as < %s | llc -march=arm | grep bl.*quux | wc -l | grep 1
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; RUN: llvm-as < %s | llc -march=arm -enable-tail-merge=0 | grep bl.*baz | wc -l | grep 2
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; RUN: llvm-as < %s | llc -march=arm -enable-tail-merge=0 | grep bl.*quux | wc -l | grep 2
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; Check that tail merging is the default on ARM, and that -enable-tail-merge=0 works.
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; ModuleID = 'tail.c'
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
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target triple = "i686-apple-darwin8"
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define i32 @f(i32 %i, i32 %q) {
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entry:
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%i_addr = alloca i32 ; <i32*> [#uses=2]
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%q_addr = alloca i32 ; <i32*> [#uses=2]
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%retval = alloca i32, align 4 ; <i32*> [#uses=1]
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"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
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store i32 %i, i32* %i_addr
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store i32 %q, i32* %q_addr
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%tmp = load i32* %i_addr ; <i32> [#uses=1]
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%tmp1 = icmp ne i32 %tmp, 0 ; <i1> [#uses=1]
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%tmp12 = zext i1 %tmp1 to i8 ; <i8> [#uses=1]
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%toBool = icmp ne i8 %tmp12, 0 ; <i1> [#uses=1]
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br i1 %toBool, label %cond_true, label %cond_false
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cond_true: ; preds = %entry
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%tmp3 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
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%tmp4 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
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%tmp7 = load i32* %q_addr ; <i32> [#uses=1]
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%tmp8 = icmp ne i32 %tmp7, 0 ; <i1> [#uses=1]
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%tmp89 = zext i1 %tmp8 to i8 ; <i8> [#uses=1]
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%toBool10 = icmp ne i8 %tmp89, 0 ; <i1> [#uses=1]
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br i1 %toBool10, label %cond_true11, label %cond_false15
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cond_false: ; preds = %entry
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%tmp5 = call i32 (...)* @foo( ) ; <i32> [#uses=0]
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%tmp6 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
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%tmp27 = load i32* %q_addr ; <i32> [#uses=1]
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%tmp28 = icmp ne i32 %tmp27, 0 ; <i1> [#uses=1]
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%tmp289 = zext i1 %tmp28 to i8 ; <i8> [#uses=1]
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%toBool210 = icmp ne i8 %tmp289, 0 ; <i1> [#uses=1]
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br i1 %toBool210, label %cond_true11, label %cond_false15
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cond_true11: ; preds = %cond_next
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%tmp13 = call i32 (...)* @foo( ) ; <i32> [#uses=0]
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%tmp14 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0]
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br label %cond_next18
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cond_false15: ; preds = %cond_next
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%tmp16 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
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%tmp17 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0]
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br label %cond_next18
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cond_next18: ; preds = %cond_false15, %cond_true11
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%tmp19 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
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br label %return
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return: ; preds = %cond_next18
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%retval20 = load i32* %retval ; <i32> [#uses=1]
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ret i32 %retval20
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}
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declare i32 @bar(...)
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declare i32 @baz(...)
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declare i32 @foo(...)
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declare i32 @quux(...)
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68
test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll
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68
test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll
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@ -0,0 +1,68 @@
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; RUN: llvm-as < %s | llc -march=ppc32 | grep bl.*baz | wc -l | grep 2
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; RUN: llvm-as < %s | llc -march=ppc32 | grep bl.*quux | wc -l | grep 2
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; RUN: llvm-as < %s | llc -march=ppc32 -enable-tail-merge | grep bl.*baz | wc -l | grep 1
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; RUN: llvm-as < %s | llc -march=ppc32 -enable-tail-merge=1 | grep bl.*quux | wc -l | grep 1
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; Check that tail merging is not the default on ppc, and that -enable-tail-merge works.
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; ModuleID = 'tail.c'
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
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target triple = "i686-apple-darwin8"
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define i32 @f(i32 %i, i32 %q) {
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entry:
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%i_addr = alloca i32 ; <i32*> [#uses=2]
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%q_addr = alloca i32 ; <i32*> [#uses=2]
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%retval = alloca i32, align 4 ; <i32*> [#uses=1]
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"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
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store i32 %i, i32* %i_addr
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store i32 %q, i32* %q_addr
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%tmp = load i32* %i_addr ; <i32> [#uses=1]
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%tmp1 = icmp ne i32 %tmp, 0 ; <i1> [#uses=1]
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%tmp12 = zext i1 %tmp1 to i8 ; <i8> [#uses=1]
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%toBool = icmp ne i8 %tmp12, 0 ; <i1> [#uses=1]
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br i1 %toBool, label %cond_true, label %cond_false
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cond_true: ; preds = %entry
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%tmp3 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
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%tmp4 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
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%tmp7 = load i32* %q_addr ; <i32> [#uses=1]
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%tmp8 = icmp ne i32 %tmp7, 0 ; <i1> [#uses=1]
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%tmp89 = zext i1 %tmp8 to i8 ; <i8> [#uses=1]
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%toBool10 = icmp ne i8 %tmp89, 0 ; <i1> [#uses=1]
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br i1 %toBool10, label %cond_true11, label %cond_false15
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cond_false: ; preds = %entry
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%tmp5 = call i32 (...)* @foo( ) ; <i32> [#uses=0]
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%tmp6 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0]
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%tmp27 = load i32* %q_addr ; <i32> [#uses=1]
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%tmp28 = icmp ne i32 %tmp27, 0 ; <i1> [#uses=1]
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%tmp289 = zext i1 %tmp28 to i8 ; <i8> [#uses=1]
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%toBool210 = icmp ne i8 %tmp289, 0 ; <i1> [#uses=1]
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br i1 %toBool210, label %cond_true11, label %cond_false15
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cond_true11: ; preds = %cond_next
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%tmp13 = call i32 (...)* @foo( ) ; <i32> [#uses=0]
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%tmp14 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0]
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br label %cond_next18
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cond_false15: ; preds = %cond_next
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%tmp16 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
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%tmp17 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0]
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br label %cond_next18
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cond_next18: ; preds = %cond_false15, %cond_true11
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%tmp19 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
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br label %return
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return: ; preds = %cond_next18
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%retval20 = load i32* %retval ; <i32> [#uses=1]
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ret i32 %retval20
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}
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declare i32 @bar(...)
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declare i32 @baz(...)
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declare i32 @foo(...)
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declare i32 @quux(...)
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