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Add support for NEON VMVN immediate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108324 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
parent
046afdb50b
commit
7e3f0d2690
@ -625,6 +625,7 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
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case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
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case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
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case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
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case ARMISD::VDUP: return "ARMISD::VDUP";
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case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
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case ARMISD::VEXT: return "ARMISD::VEXT";
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@ -2925,6 +2926,8 @@ static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
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switch (SplatBitSize) {
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case 8:
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if (!isVMOV)
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return SDValue();
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// Any 1-byte value is OK. Op=0, Cmode=1110.
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assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
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OpCmode = 0xe;
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@ -3006,9 +3009,9 @@ static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
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return SDValue();
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case 64: {
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// NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
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if (!isVMOV)
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return SDValue();
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// NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
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uint64_t BitMask = 0xff;
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uint64_t Val = 0;
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unsigned ImmMask = 1;
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@ -3248,6 +3251,17 @@ static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
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SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
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return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
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}
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// Try an immediate VMVN.
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uint64_t NegatedImm = (SplatBits.getZExtValue() ^
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((1LL << SplatBitSize) - 1));
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Val = isNEONModifiedImm(NegatedImm,
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SplatUndef.getZExtValue(), SplatBitSize,
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DAG, VmovVT, VT.is128BitVector(), false);
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if (Val.getNode()) {
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SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
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return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
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}
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}
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}
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@ -4232,14 +4246,15 @@ static SDValue PerformVMOVRRDCombine(SDNode *N,
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/// ARMISD::VDUPLANE.
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static SDValue PerformVDUPLANECombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI) {
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// If the source is already a VMOVIMM splat, the VDUPLANE is redundant.
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// If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
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// redundant.
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SDValue Op = N->getOperand(0);
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EVT VT = N->getValueType(0);
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// Ignore bit_converts.
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while (Op.getOpcode() == ISD::BIT_CONVERT)
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Op = Op.getOperand(0);
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if (Op.getOpcode() != ARMISD::VMOVIMM)
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if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
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return SDValue();
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// Make sure the VMOV element size is not bigger than the VDUPLANE elements.
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@ -124,8 +124,11 @@ namespace llvm {
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VGETLANEu, // zero-extend vector extract element
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VGETLANEs, // sign-extend vector extract element
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// Vector duplicate:
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// Vector move immediate and move negated immediate:
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VMOVIMM,
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VMVNIMM,
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// Vector duplicate:
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VDUP,
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VDUPLANE,
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@ -65,9 +65,10 @@ def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
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def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
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def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
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def NEONvmovImm : SDNode<"ARMISD::VMOVIMM",
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SDTypeProfile<1, 1, [SDTCisVec<0>,
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SDTCisVT<1, i32>]>>;
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def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
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def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
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def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
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def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
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// VDUPLANE can produce a quad-register result from a double-register source,
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@ -2383,6 +2384,28 @@ def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
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[(set QPR:$dst, (v4i32 (or QPR:$src1,
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(vnotq QPR:$src2))))]>;
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// VMVN : Vector Bitwise NOT (Immediate)
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let isReMaterializable = 1 in {
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def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$dst),
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(ins nModImm:$SIMM), IIC_VMOVImm,
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"vmvn", "i16", "$dst, $SIMM", "",
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[(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]>;
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def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$dst),
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(ins nModImm:$SIMM), IIC_VMOVImm,
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"vmvn", "i16", "$dst, $SIMM", "",
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[(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]>;
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def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$dst),
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(ins nModImm:$SIMM), IIC_VMOVImm,
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"vmvn", "i32", "$dst, $SIMM", "",
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[(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]>;
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def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$dst),
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(ins nModImm:$SIMM), IIC_VMOVImm,
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"vmvn", "i32", "$dst, $SIMM", "",
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[(set QPR:$dst, (v4i32 (NEONvmvnImm timm:$SIMM)))]>;
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}
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// VMVN : Vector Bitwise NOT
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def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
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(outs DPR:$dst), (ins DPR:$src), IIC_VSUBiD,
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@ -18,6 +18,18 @@ define <4 x i16> @v_movi16b() nounwind {
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ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
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}
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define <4 x i16> @v_mvni16a() nounwind {
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;CHECK: v_mvni16a:
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;CHECK: vmvn.i16 d0, #0x10
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ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
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}
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define <4 x i16> @v_mvni16b() nounwind {
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;CHECK: v_mvni16b:
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;CHECK: vmvn.i16 d0, #0x1000
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ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
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}
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define <2 x i32> @v_movi32a() nounwind {
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;CHECK: v_movi32a:
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;CHECK: vmov.i32 d0, #0x20
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@ -54,6 +66,42 @@ define <2 x i32> @v_movi32f() nounwind {
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ret <2 x i32> < i32 2162687, i32 2162687 >
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}
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define <2 x i32> @v_mvni32a() nounwind {
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;CHECK: v_mvni32a:
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;CHECK: vmvn.i32 d0, #0x20
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ret <2 x i32> < i32 4294967263, i32 4294967263 >
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}
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define <2 x i32> @v_mvni32b() nounwind {
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;CHECK: v_mvni32b:
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;CHECK: vmvn.i32 d0, #0x2000
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ret <2 x i32> < i32 4294959103, i32 4294959103 >
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}
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define <2 x i32> @v_mvni32c() nounwind {
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;CHECK: v_mvni32c:
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;CHECK: vmvn.i32 d0, #0x200000
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ret <2 x i32> < i32 4292870143, i32 4292870143 >
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}
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define <2 x i32> @v_mvni32d() nounwind {
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;CHECK: v_mvni32d:
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;CHECK: vmvn.i32 d0, #0x20000000
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ret <2 x i32> < i32 3758096383, i32 3758096383 >
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}
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define <2 x i32> @v_mvni32e() nounwind {
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;CHECK: v_mvni32e:
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;CHECK: vmvn.i32 d0, #0x20FF
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ret <2 x i32> < i32 4294958848, i32 4294958848 >
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}
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define <2 x i32> @v_mvni32f() nounwind {
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;CHECK: v_mvni32f:
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;CHECK: vmvn.i32 d0, #0x20FFFF
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ret <2 x i32> < i32 4292804608, i32 4292804608 >
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}
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define <1 x i64> @v_movi64() nounwind {
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;CHECK: v_movi64:
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;CHECK: vmov.i64 d0, #0xFF0000FF0000FFFF
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