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[globalisel][tablegen] Require that all registers between instructions of a match are virtual.

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Summary:
Without this, it's possible to encounter multiple defs for a register.

This is triggered by the current version of D32868 when applied to trunk.

Reviewers: qcolombet, ab, t.p.northover, rovka, kristof.beyls

Reviewed By: qcolombet

Subscribers: llvm-commits, igorb

Differential Revision: https://reviews.llvm.org/D32869

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303253 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2017-05-17 12:43:30 +00:00
parent 663da44a76
commit 7e6b531c1a
2 changed files with 6 additions and 0 deletions
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4
test/TableGen/GlobalISelEmitter.td
View File

@ -138,6 +138,8 @@ def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2),
// CHECK-NEXT: return false;
// CHECK-NEXT: if (!MI0.getOperand(1).isReg())
// CHECK-NEXT: return false;
// CHECK-NEXT: if (TRI.isPhysicalRegister(MI0.getOperand(1).getReg()))
// CHECK-NEXT: return false;
// CHECK-NEXT: MachineInstr &MI1 = *MRI.getVRegDef(MI0.getOperand(1).getReg());
// CHECK-NEXT: if (MI1.getNumOperands() < 3)
// CHECK-NEXT: return false;
@ -180,6 +182,8 @@ def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2),
// CHECK-NEXT: return false;
// CHECK-NEXT: if (!MI0.getOperand(2).isReg())
// CHECK-NEXT: return false;
// CHECK-NEXT: if (TRI.isPhysicalRegister(MI0.getOperand(2).getReg()))
// CHECK-NEXT: return false;
// CHECK-NEXT: MachineInstr &MI1 = *MRI.getVRegDef(MI0.getOperand(2).getReg());
// CHECK-NEXT: if (MI1.getNumOperands() < 3)
// CHECK-NEXT: return false;

2
utils/TableGen/GlobalISelEmitter.cpp
View File

@ -775,6 +775,8 @@ public:
void emitCxxCaptureStmts(raw_ostream &OS, RuleMatcher &Rule,
StringRef OperandExpr) const override {
OS << "if (!" << OperandExpr + ".isReg())\n"
<< " return false;\n"
<< "if (TRI.isPhysicalRegister(" << OperandExpr + ".getReg()))\n"
<< " return false;\n";
std::string InsnVarName = Rule.defineInsnVar(
OS, *InsnMatcher,