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[mips] Tolerate the use of the %z inline asm operand modifier with non-immediates.

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Summary:
Currently, we give an error if %z is used with non-immediates, instead of continuing as if the %z isn't there.

For example, you use the %z operand modifier along with the "Jr" constraints ("r" makes the operand a register, and "J" makes it an immediate, but only if its value is 0). 
In this case, you want the compiler to print "$0" if the inline asm input operand turns out to be an immediate zero and you want it to print the register containing the operand, if it's not.

We give an error in the latter case, and we shouldn't (GCC also doesn't).

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6023

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221453 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Toma Tabacu 2014-11-06 14:25:42 +00:00
parent 2b8f96996b
commit 7f22a20351
2 changed files with 32 additions and 7 deletions
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12
lib/Target/Mips/MipsAsmPrinter.cpp
View File

@ -473,14 +473,12 @@ bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
return false; return false;
case 'z': { case 'z': {
// $0 if zero, regular printing otherwise // $0 if zero, regular printing otherwise
if (MO.getType() != MachineOperand::MO_Immediate) if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 0) {
return true;
int64_t Val = MO.getImm();
if (Val)
O << Val;
else
O << "$0"; O << "$0";
return false; return false;
}
// If not, call printOperand as normal.
break;
} }
case 'D': // Second part of a double word register operand case 'D': // Second part of a double word register operand
case 'L': // Low order register of a double word register operand case 'L': // Low order register of a double word register operand

27
test/CodeGen/Mips/inlineasm-operand-code.ll
View File

@ -65,6 +65,33 @@ entry:
;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},$0 ;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},$0
;CHECK_LITTLE_32: #NO_APP ;CHECK_LITTLE_32: #NO_APP
tail call i32 asm sideeffect "addiu $0,$1,${2:z}", "=r,r,I"(i32 7, i32 0) nounwind tail call i32 asm sideeffect "addiu $0,$1,${2:z}", "=r,r,I"(i32 7, i32 0) nounwind
; z with non-zero and the "r"(register) and "J"(integer zero) constraints
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
;CHECK_LITTLE_32: #NO_APP
call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 7) nounwind
; z with zero and the "r"(register) and "J"(integer zero) constraints
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: mtc0 $0, ${{[0-9]+}}
;CHECK_LITTLE_32: #NO_APP
call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 0) nounwind
; z with non-zero and just the "r"(register) constraint
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
;CHECK_LITTLE_32: #NO_APP
call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 7) nounwind
; z with zero and just the "r"(register) constraint
; FIXME: Check for $0, instead of other registers.
; We should be using $0 directly in this case, not real registers.
; When the materialization of 0 gets fixed, this test will fail.
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
;CHECK_LITTLE_32: #NO_APP
call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 0) nounwind
ret i32 0 ret i32 0
} }