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[DAG] Don't increase SDNodeOrder for dbg.value/declare.
Summary: The SDNodeOrder is saved in the IROrder field in the SDNode, and this field may affects scheduling. Thus, letting dbg.value/declare increase the order numbers may in turn affect scheduling. Because of this change we also need to update the code deciding when dbg values should be output, in ScheduleDAGSDNodes.cpp/ProcessSDDbgValues. Dbg values now have the same order as the SDNode they are connected to, not the following orders. Test cases provided by Florian Hahn. Reviewers: bogner, aprantl, sunfish, atrick Reviewed By: atrick Subscribers: fhahn, probinson, andreadb, llvm-commits, MatzeB Differential Revision: https://reviews.llvm.org/D25318 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292485 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Mikael Holmen
parent
08536b81ae
commit
7f6f824722
@ -704,8 +704,8 @@ ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
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if (!N->getHasDebugValue())
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return;
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// Opportunistically insert immediate dbg_value uses, i.e. those with source
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// order number right after the N.
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// Opportunistically insert immediate dbg_value uses, i.e. those with the same
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// source order number as N.
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MachineBasicBlock *BB = Emitter.getBlock();
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MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos();
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ArrayRef<SDDbgValue*> DVs = DAG->GetDbgValues(N);
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@ -713,7 +713,7 @@ ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
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if (DVs[i]->isInvalidated())
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continue;
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unsigned DVOrder = DVs[i]->getOrder();
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if (!Order || DVOrder == ++Order) {
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if (!Order || DVOrder == Order) {
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MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], VRBaseMap);
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if (DbgMI) {
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Orders.push_back(std::make_pair(DVOrder, DbgMI));
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@ -937,7 +937,9 @@ void SelectionDAGBuilder::visit(const Instruction &I) {
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HandlePHINodesInSuccessorBlocks(I.getParent());
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}
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++SDNodeOrder;
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// Increase the SDNodeOrder if dealing with a non-debug instruction.
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if (!isa<DbgInfoIntrinsic>(I))
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++SDNodeOrder;
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CurInst = &I;
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96
test/CodeGen/AArch64/selectiondag-order.ll
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96
test/CodeGen/AArch64/selectiondag-order.ll
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@ -0,0 +1,96 @@
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; Check that debug intrinsics do not affect code generation.
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; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mattr=+avx | FileCheck --check-prefix=AARCH64-CHECK %s
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define i64 @simulate(<2 x i32> %a) {
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entry:
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%rand = tail call i64 @lrand48()
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br label %body
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body: ; preds = %body, %entry
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%0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ]
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%add = add <2 x i32> %0, %a
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%rand1 = tail call i64 @lrand48() #3
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%cmp = icmp eq i64 %rand1, 0
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br i1 %cmp, label %end, label %body
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end: ; preds = %body
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%c = bitcast <2 x i32> %add to i64
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%res = add i64 %rand, %c
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ret i64 %res
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}
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; AARCH64-CHECK: simulate:
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; AARCH64-CHECK: movi d9, #0000000000000000
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; AARCH64-CHECK: bl lrand48
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; AARCH64-CHECK: mov x19, x0
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; AARCH64-CHECK: BB0_1:
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define i64 @simulateWithDebugIntrinsic(<2 x i32> %a) local_unnamed_addr {
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entry:
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%rand = tail call i64 @lrand48() #3
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tail call void @llvm.dbg.value(metadata i64 %rand, i64 0, metadata !6, metadata !7), !dbg !8
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br label %body
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body: ; preds = %body, %entry
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%0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ]
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%add = add <2 x i32> %0, %a
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%rand1 = tail call i64 @lrand48() #3
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%cmp = icmp eq i64 %rand1, 0
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br i1 %cmp, label %end, label %body
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end: ; preds = %body
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%c = bitcast <2 x i32> %add to i64
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%res = add i64 %rand, %c
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ret i64 %res
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}
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; AARCH64-CHECK: simulateWithDebugIntrinsic
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; AARCH64-CHECK: movi d9, #0000000000000000
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; AARCH64-CHECK: bl lrand48
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; AARCH64-CHECK: mov x19, x0
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; AARCH64-CHECK: BB1_1:
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define i64 @simulateWithDbgDeclare(<2 x i32> %a) local_unnamed_addr {
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entry:
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%rand = tail call i64 @lrand48() #3
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tail call void @llvm.dbg.declare(metadata i64 %rand, metadata !6, metadata !7), !dbg !8
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br label %body
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body: ; preds = %body, %entry
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%0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ]
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%add = add <2 x i32> %0, %a
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%rand1 = tail call i64 @lrand48() #3
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%cmp = icmp eq i64 %rand1, 0
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br i1 %cmp, label %end, label %body
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end: ; preds = %body
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%c = bitcast <2 x i32> %add to i64
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%res = add i64 %rand, %c
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ret i64 %res
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}
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; AARCH64-CHECK: simulateWithDbgDeclare:
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; AARCH64-CHECK: movi d9, #0000000000000000
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; AARCH64-CHECK: bl lrand48
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; AARCH64-CHECK: mov x19, x0
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; AARCH64-CHECK: BB2_1:
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declare i64 @lrand48()
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declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
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declare void @llvm.dbg.declare(metadata, metadata, metadata)
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!llvm.dbg.cu = !{!1}
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!llvm.module.flags = !{!3, !4}
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!1 = distinct !DICompileUnit(language: DW_LANG_C99, file: !2, runtimeVersion: 0, emissionKind: FullDebug)
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!2 = !DIFile(filename: "test.ll", directory: ".")
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!3 = !{i32 2, !"Dwarf Version", i32 4}
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!4 = !{i32 2, !"Debug Info Version", i32 3}
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!5 = distinct !DISubprogram(name: "simulateWithDebugIntrinsic", scope: !2, file: !2, line: 64, isLocal: false, isDefinition: true, scopeLine: 65, unit: !1)
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!6 = !DILocalVariable(name: "randv", scope: !5, file: !2, line: 69)
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!7 = !DIExpression()
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!8 = !DILocation(line: 132, column: 2, scope: !5)
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97
test/CodeGen/X86/selectiondag-order.ll
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97
test/CodeGen/X86/selectiondag-order.ll
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@ -0,0 +1,97 @@
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; Check that debug intrinsics do not affect code generation.
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck --check-prefix=X86-CHECK %s
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define i64 @simulate(<2 x i32> %a) {
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entry:
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%rand = tail call i64 @lrand48()
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br label %body
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body: ; preds = %body, %entry
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%0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ]
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%add = add <2 x i32> %0, %a
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%rand1 = tail call i64 @lrand48() #3
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%cmp = icmp eq i64 %rand1, 0
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br i1 %cmp, label %end, label %body
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end: ; preds = %body
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%c = bitcast <2 x i32> %add to i64
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%res = add i64 %rand, %c
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ret i64 %res
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}
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; X86-CHECK: simulate:
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; X86-CHECK: movdqa %xmm0, 16(%rsp)
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; X86-CHECK: pxor %xmm0, %xmm0
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; X86-CHECK: movdqa %xmm0, (%rsp)
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; X86-CHECK: callq lrand48
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; X86-CHECK: movq %rax, %rbx
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define i64 @simulateWithDebugIntrinsic(<2 x i32> %a) local_unnamed_addr {
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entry:
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%rand = tail call i64 @lrand48() #3
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tail call void @llvm.dbg.value(metadata i64 %rand, i64 0, metadata !6, metadata !7), !dbg !8
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br label %body
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body: ; preds = %body, %entry
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%0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ]
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%add = add <2 x i32> %0, %a
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%rand1 = tail call i64 @lrand48() #3
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%cmp = icmp eq i64 %rand1, 0
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br i1 %cmp, label %end, label %body
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end: ; preds = %body
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%c = bitcast <2 x i32> %add to i64
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%res = add i64 %rand, %c
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ret i64 %res
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}
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; X86-CHECK: simulateWithDebugIntrinsic:
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; X86-CHECK: movdqa %xmm0, 16(%rsp)
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; X86-CHECK: pxor %xmm0, %xmm0
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; X86-CHECK: movdqa %xmm0, (%rsp)
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; X86-CHECK: callq lrand48
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; X86-CHECK: movq %rax, %rbx
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define i64 @simulateWithDbgDeclare(<2 x i32> %a) local_unnamed_addr {
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entry:
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%rand = tail call i64 @lrand48() #3
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tail call void @llvm.dbg.declare(metadata i64 %rand, metadata !6, metadata !7), !dbg !8
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br label %body
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body: ; preds = %body, %entry
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%0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ]
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%add = add <2 x i32> %0, %a
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%rand1 = tail call i64 @lrand48() #3
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%cmp = icmp eq i64 %rand1, 0
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br i1 %cmp, label %end, label %body
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end: ; preds = %body
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%c = bitcast <2 x i32> %add to i64
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%res = add i64 %rand, %c
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ret i64 %res
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}
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; X86-CHECK: simulateWithDbgDeclare:
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; X86-CHECK: movdqa %xmm0, 16(%rsp)
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; X86-CHECK: pxor %xmm0, %xmm0
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; X86-CHECK: movdqa %xmm0, (%rsp)
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; X86-CHECK: callq lrand48
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; X86-CHECK: movq %rax, %rbx
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declare i64 @lrand48()
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declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
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declare void @llvm.dbg.declare(metadata, metadata, metadata)
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!llvm.dbg.cu = !{!1}
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!llvm.module.flags = !{!3, !4}
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!1 = distinct !DICompileUnit(language: DW_LANG_C99, file: !2, runtimeVersion: 0, emissionKind: FullDebug)
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!2 = !DIFile(filename: "test.ll", directory: ".")
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!3 = !{i32 2, !"Dwarf Version", i32 4}
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!4 = !{i32 2, !"Debug Info Version", i32 3}
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!5 = distinct !DISubprogram(name: "simulateWithDebugIntrinsic", scope: !2, file: !2, line: 64, isLocal: false, isDefinition: true, scopeLine: 65, unit: !1)
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!6 = !DILocalVariable(name: "randv", scope: !5, file: !2, line: 69)
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!7 = !DIExpression()
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!8 = !DILocation(line: 132, column: 2, scope: !5)
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