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https://github.com/RPCSX/llvm.git
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Convert load/store over to being pattern matched
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24871 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
parent
898101c15f
commit
7fd1edd32e
@ -181,7 +181,19 @@ namespace {
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unsigned RegNo = enumRegToMachineReg(CCReg);
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O << (0x80 >> RegNo);
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}
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// The new addressing mode printers, currently empty
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void printMemRegImm(const MachineInstr *MI, unsigned OpNo) {
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printSymbolLo(MI, OpNo);
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O << '(';
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printOperand(MI, OpNo+1);
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O << ')';
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}
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void printMemRegReg(const MachineInstr *MI, unsigned OpNo) {
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printOperand(MI, OpNo);
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O << ", ";
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printOperand(MI, OpNo+1);
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}
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virtual bool runOnMachineFunction(MachineFunction &F) = 0;
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virtual bool doFinalization(Module &M) = 0;
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};
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@ -68,15 +68,18 @@ namespace {
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/// specified condition code, returning the CR# of the expression.
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SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
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/// SelectAddr - Given the specified address, return the two operands for a
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/// load/store instruction, and return true if it should be an indexed [r+r]
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/// operation.
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bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
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/// SelectAddrImm - Returns true if the address N can be represented by
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/// a base register plus a signed 16-bit displacement [r+imm].
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bool SelectAddrImm(SDOperand N, SDOperand &Disp, SDOperand &Base);
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/// SelectAddrIdx - Given the specified addressed, check to see if it can be
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/// represented as an indexed [r+r] operation. Returns false if it can
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/// be represented by [r+imm], which are preferred.
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bool SelectAddrIdx(SDOperand N, SDOperand &Base, SDOperand &Index);
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/// SelectAddrIndexed - Given the specified addressed, force it to be
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/// represented as an indexed [r+r] operation, rather than possibly
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/// returning [r+imm] as SelectAddr may.
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void SelectAddrIndexed(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
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/// SelectAddrIdxOnly - Given the specified addressed, force it to be
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/// represented as an indexed [r+r] operation.
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bool SelectAddrIdxOnly(SDOperand N, SDOperand &Base, SDOperand &Index);
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SDOperand BuildSDIVSequence(SDNode *N);
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SDOperand BuildUDIVSequence(SDNode *N);
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@ -400,65 +403,77 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
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return 0;
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}
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/// SelectAddr - Given the specified address, return the two operands for a
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/// load/store instruction, and return true if it should be an indexed [r+r]
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/// operation.
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bool PPCDAGToDAGISel::SelectAddr(SDOperand Addr, SDOperand &Op1,
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SDOperand &Op2) {
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unsigned imm = 0;
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if (Addr.getOpcode() == ISD::ADD) {
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if (isIntImmediate(Addr.getOperand(1), imm) && isInt16(imm)) {
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Op1 = getI32Imm(Lo16(imm));
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if (FrameIndexSDNode *FI =
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dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
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++FrameOff;
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Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
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/// SelectAddrImm - Returns true if the address N can be represented by
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/// a base register plus a signed 16-bit displacement [r+imm].
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bool PPCDAGToDAGISel::SelectAddrImm(SDOperand N, SDOperand &Disp,
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SDOperand &Base) {
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if (N.getOpcode() == ISD::ADD) {
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unsigned imm = 0;
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if (isIntImmediate(N.getOperand(1), imm) && isInt16(imm)) {
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Disp = getI32Imm(Lo16(imm));
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if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
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Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
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} else {
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Op2 = Select(Addr.getOperand(0));
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Base = Select(N.getOperand(0));
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}
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return false;
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} else if (Addr.getOperand(1).getOpcode() == PPCISD::Lo) {
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return true; // [r+i]
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} else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
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// Match LOAD (ADD (X, Lo(G))).
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assert(!cast<ConstantSDNode>(Addr.getOperand(1).getOperand(1))->getValue()
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assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
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&& "Cannot handle constant offsets yet!");
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Op1 = Addr.getOperand(1).getOperand(0); // The global address.
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assert(Op1.getOpcode() == ISD::TargetGlobalAddress ||
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Op1.getOpcode() == ISD::TargetConstantPool);
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Op2 = Select(Addr.getOperand(0));
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return false; // [&g+r]
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} else {
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Op1 = Select(Addr.getOperand(0));
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Op2 = Select(Addr.getOperand(1));
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return true; // [r+r]
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Disp = N.getOperand(1).getOperand(0); // The global address.
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assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
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Disp.getOpcode() == ISD::TargetConstantPool);
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Base = Select(N.getOperand(0));
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return true; // [&g+r]
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}
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return false; // [r+r]
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}
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if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr))
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Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
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Disp = getI32Imm(0);
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if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
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Base = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
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else
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Op2 = Select(Addr);
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Op1 = getI32Imm(0);
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return false;
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Base = Select(N);
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return true; // [r+0]
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}
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/// SelectAddrIndexed - Given the specified addressed, force it to be
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/// represented as an indexed [r+r] operation, rather than possibly
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/// returning [r+imm] as SelectAddr may.
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void PPCDAGToDAGISel::SelectAddrIndexed(SDOperand Addr, SDOperand &Op1,
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SDOperand &Op2) {
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if (Addr.getOpcode() == ISD::ADD) {
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Op1 = Select(Addr.getOperand(0));
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Op2 = Select(Addr.getOperand(1));
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return;
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/// SelectAddrIdx - Given the specified addressed, check to see if it can be
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/// represented as an indexed [r+r] operation. Returns false if it can
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/// be represented by [r+imm], which are preferred.
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bool PPCDAGToDAGISel::SelectAddrIdx(SDOperand N, SDOperand &Base,
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SDOperand &Index) {
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// Check to see if we can represent this as an [r+imm] address instead,
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// which will fail if the address is more profitably represented as an
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// [r+r] address.
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if (SelectAddrImm(N, Base, Index))
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return false;
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if (N.getOpcode() == ISD::ADD) {
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Base = Select(N.getOperand(0));
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Index = Select(N.getOperand(1));
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return true;
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}
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// FIXME: This should be a CopyFromReg R0 rather than a load of 0.
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Base = CurDAG->getTargetNode(PPC::LI, MVT::i32, getI32Imm(0));
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Index = Select(N);
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return true;
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}
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/// SelectAddrIdxOnly - Given the specified addressed, force it to be
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/// represented as an indexed [r+r] operation.
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bool PPCDAGToDAGISel::SelectAddrIdxOnly(SDOperand N, SDOperand &Base,
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SDOperand &Index) {
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if (N.getOpcode() == ISD::ADD) {
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Base = Select(N.getOperand(0));
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Index = Select(N.getOperand(1));
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return true;
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}
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if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr)) {
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Op1 = CurDAG->getTargetNode(PPC::LI, MVT::i32, getI32Imm(0));
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Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
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return;
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}
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Op1 = CurDAG->getTargetNode(PPC::LI, MVT::i32, getI32Imm(0));
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Op2 = Select(Addr);
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// FIXME: This should be a CopyFromReg R0 rather than a load of 0.
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Base = CurDAG->getTargetNode(PPC::LI, MVT::i32, getI32Imm(0));
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Index = Select(N);
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return true;
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}
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/// SelectCC - Select a comparison of the specified values with the specified
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@ -997,95 +1012,6 @@ SDOperand PPCDAGToDAGISel::Select(SDOperand Op) {
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// Other cases are autogenerated.
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break;
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}
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case ISD::LOAD:
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case ISD::EXTLOAD:
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case ISD::ZEXTLOAD:
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case ISD::SEXTLOAD: {
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SDOperand Op1, Op2;
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// If this is a vector load, then force this to be indexed addressing, since
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// altivec does not have immediate offsets for loads.
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bool isIdx = true;
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if (N->getOpcode() == ISD::LOAD && MVT::isVector(N->getValueType(0))) {
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SelectAddrIndexed(N->getOperand(1), Op1, Op2);
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} else {
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isIdx = SelectAddr(N->getOperand(1), Op1, Op2);
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}
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MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
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N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
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unsigned Opc;
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switch (TypeBeingLoaded) {
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default: N->dump(); assert(0 && "Cannot load this type!");
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case MVT::i1:
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case MVT::i8: Opc = isIdx ? PPC::LBZX : PPC::LBZ; break;
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case MVT::i16:
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if (N->getOpcode() == ISD::SEXTLOAD) { // SEXT load?
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Opc = isIdx ? PPC::LHAX : PPC::LHA;
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} else {
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Opc = isIdx ? PPC::LHZX : PPC::LHZ;
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}
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break;
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case MVT::i32: Opc = isIdx ? PPC::LWZX : PPC::LWZ; break;
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case MVT::f32: Opc = isIdx ? PPC::LFSX : PPC::LFS; break;
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case MVT::f64: Opc = isIdx ? PPC::LFDX : PPC::LFD; break;
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case MVT::v4f32: Opc = PPC::LVX; break;
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}
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// If this is an f32 -> f64 load, emit the f32 load, then use an 'extending
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// copy'.
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if (TypeBeingLoaded != MVT::f32 || N->getOpcode() == ISD::LOAD) {
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return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
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Op1, Op2, Select(N->getOperand(0))).
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getValue(Op.ResNo);
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} else {
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std::vector<SDOperand> Ops;
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Ops.push_back(Op1);
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Ops.push_back(Op2);
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Ops.push_back(Select(N->getOperand(0)));
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SDOperand Res = CurDAG->getTargetNode(Opc, MVT::f32, MVT::Other, Ops);
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SDOperand Ext = CurDAG->getTargetNode(PPC::FMRSD, MVT::f64, Res);
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CodeGenMap[Op.getValue(0)] = Ext;
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CodeGenMap[Op.getValue(1)] = Res.getValue(1);
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if (Op.ResNo)
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return Res.getValue(1);
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else
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return Ext;
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}
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}
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case ISD::TRUNCSTORE:
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case ISD::STORE: {
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SDOperand AddrOp1, AddrOp2;
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// If this is a vector store, then force this to be indexed addressing,
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// since altivec does not have immediate offsets for stores.
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bool isIdx = true;
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if (N->getOpcode() == ISD::STORE &&
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MVT::isVector(N->getOperand(1).getValueType())) {
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SelectAddrIndexed(N->getOperand(2), AddrOp1, AddrOp2);
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} else {
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isIdx = SelectAddr(N->getOperand(2), AddrOp1, AddrOp2);
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}
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unsigned Opc;
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if (N->getOpcode() == ISD::STORE) {
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switch (N->getOperand(1).getValueType()) {
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default: assert(0 && "unknown Type in store");
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case MVT::i32: Opc = isIdx ? PPC::STWX : PPC::STW; break;
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case MVT::f64: Opc = isIdx ? PPC::STFDX : PPC::STFD; break;
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case MVT::f32: Opc = isIdx ? PPC::STFSX : PPC::STFS; break;
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case MVT::v4f32: Opc = PPC::STVX;
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}
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} else { //ISD::TRUNCSTORE
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switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
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default: assert(0 && "unknown Type in store");
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case MVT::i8: Opc = isIdx ? PPC::STBX : PPC::STB; break;
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case MVT::i16: Opc = isIdx ? PPC::STHX : PPC::STH; break;
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}
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}
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return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(1)),
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AddrOp1, AddrOp2, Select(N->getOperand(0)));
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}
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case ISD::SELECT_CC: {
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ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
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@ -126,6 +126,7 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
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// FIXME: AltiVec supports a wide variety of packed types. For now, we're
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// bringing up support with just v4f32.
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addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
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addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
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}
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setSetCCResultContents(ZeroOrOneSetCCResult);
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@ -165,6 +165,22 @@ def symbolLo: Operand<i32> {
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def crbitm: Operand<i8> {
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let PrintMethod = "printcrbitm";
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}
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// Address operands
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def memri : Operand<i32> {
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let PrintMethod = "printMemRegImm";
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let NumMIOperands = 2;
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let MIOperandInfo = (ops i32imm, GPRC);
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}
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def memrr : Operand<i32> {
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let PrintMethod = "printMemRegReg";
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let NumMIOperands = 2;
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let MIOperandInfo = (ops GPRC, GPRC);
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}
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// Define X86 specific addressing mode.
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def iaddr : ComplexPattern<i32, 2, "SelectAddrImm", []>;
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def xaddr : ComplexPattern<i32, 2, "SelectAddrIdx", []>;
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def xoaddr : ComplexPattern<i32, 2, "SelectAddrIdxOnly",[]>;
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//===----------------------------------------------------------------------===//
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// PowerPC Instruction Predicate Definitions.
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@ -258,21 +274,21 @@ let isCall = 1,
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// register and an immediate are of this type.
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//
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let isLoad = 1 in {
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def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
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"lbz $rD, $disp($rA)", LdStGeneral,
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[]>;
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def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
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"lha $rD, $disp($rA)", LdStLHA,
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[]>;
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def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
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"lhz $rD, $disp($rA)", LdStGeneral,
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[]>;
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def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
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"lbz $rD, $src", LdStGeneral,
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[(set GPRC:$rD, (zextload iaddr:$src, i8))]>;
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def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src),
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"lha $rD, $src", LdStLHA,
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[(set GPRC:$rD, (sextload iaddr:$src, i16))]>;
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def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
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"lhz $rD, $src", LdStGeneral,
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[(set GPRC:$rD, (zextload iaddr:$src, i16))]>;
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def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
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"lmw $rD, $disp($rA)", LdStLMW,
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[]>;
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def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
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"lwz $rD, $disp($rA)", LdStGeneral,
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[]>;
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def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
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"lwz $rD, $src", LdStGeneral,
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[(set GPRC:$rD, (load iaddr:$src))]>;
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def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
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"lwzu $rD, $disp($rA)", LdStGeneral,
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[]>;
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@ -309,15 +325,15 @@ let isStore = 1 in {
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def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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"stmw $rS, $disp($rA)", LdStLMW,
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[]>;
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def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
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"stb $rS, $disp($rA)", LdStGeneral,
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[]>;
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def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
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"sth $rS, $disp($rA)", LdStGeneral,
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[]>;
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def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
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"stw $rS, $disp($rA)", LdStGeneral,
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[]>;
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def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
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"stb $rS, $src", LdStGeneral,
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[(truncstore GPRC:$rS, iaddr:$src, i8)]>;
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def STH : DForm_3<44, (ops GPRC:$rS, memri:$src),
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"sth $rS, $src", LdStGeneral,
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[(truncstore GPRC:$rS, iaddr:$src, i16)]>;
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def STW : DForm_3<36, (ops GPRC:$rS, memri:$src),
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"stw $rS, $src", LdStGeneral,
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[(store GPRC:$rS, iaddr:$src)]>;
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def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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"stwu $rS, $disp($rA)", LdStGeneral,
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[]>;
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@ -355,20 +371,20 @@ def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
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def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
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"cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
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||||
let isLoad = 1 in {
|
||||
def LFS : DForm_8<48, (ops F4RC:$rD, symbolLo:$disp, GPRC:$rA),
|
||||
"lfs $rD, $disp($rA)", LdStLFDU,
|
||||
[]>;
|
||||
def LFD : DForm_8<50, (ops F8RC:$rD, symbolLo:$disp, GPRC:$rA),
|
||||
"lfd $rD, $disp($rA)", LdStLFD,
|
||||
[]>;
|
||||
def LFS : DForm_8<48, (ops F4RC:$rD, memri:$src),
|
||||
"lfs $rD, $src", LdStLFDU,
|
||||
[(set F4RC:$rD, (load iaddr:$src))]>;
|
||||
def LFD : DForm_8<50, (ops F8RC:$rD, memri:$src),
|
||||
"lfd $rD, $src", LdStLFD,
|
||||
[(set F8RC:$rD, (load iaddr:$src))]>;
|
||||
}
|
||||
let isStore = 1 in {
|
||||
def STFS : DForm_9<52, (ops F4RC:$rS, symbolLo:$disp, GPRC:$rA),
|
||||
"stfs $rS, $disp($rA)", LdStUX,
|
||||
[]>;
|
||||
def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA),
|
||||
"stfd $rS, $disp($rA)", LdStUX,
|
||||
[]>;
|
||||
def STFS : DForm_9<52, (ops F4RC:$rS, memri:$dst),
|
||||
"stfs $rS, $dst", LdStUX,
|
||||
[(store F4RC:$rS, iaddr:$dst)]>;
|
||||
def STFD : DForm_9<54, (ops F8RC:$rS, memri:$dst),
|
||||
"stfd $rS, $dst", LdStUX,
|
||||
[(store F8RC:$rS, iaddr:$dst)]>;
|
||||
}
|
||||
|
||||
// DS-Form instructions. Load/Store instructions available in PPC-64
|
||||
@ -394,24 +410,24 @@ def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
|
||||
// register and another register are of this type.
|
||||
//
|
||||
let isLoad = 1 in {
|
||||
def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
|
||||
"lbzx $dst, $base, $index", LdStGeneral,
|
||||
[]>;
|
||||
def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
|
||||
"lhax $dst, $base, $index", LdStLHA,
|
||||
[]>;
|
||||
def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
|
||||
"lhzx $dst, $base, $index", LdStGeneral,
|
||||
[]>;
|
||||
def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
|
||||
"lwax $dst, $base, $index", LdStLHA,
|
||||
[]>, isPPC64;
|
||||
def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
|
||||
"lwzx $dst, $base, $index", LdStGeneral,
|
||||
[]>;
|
||||
def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
|
||||
"ldx $dst, $base, $index", LdStLD,
|
||||
[]>, isPPC64;
|
||||
def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
|
||||
"lbzx $rD, $src", LdStGeneral,
|
||||
[(set GPRC:$rD, (zextload xaddr:$src, i8))]>;
|
||||
def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src),
|
||||
"lhax $rD, $src", LdStLHA,
|
||||
[(set GPRC:$rD, (sextload xaddr:$src, i16))]>;
|
||||
def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src),
|
||||
"lhzx $rD, $src", LdStGeneral,
|
||||
[(set GPRC:$rD, (zextload xaddr:$src, i16))]>;
|
||||
def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src),
|
||||
"lwax $rD, $src", LdStLHA,
|
||||
[(set G8RC:$rD, (sextload xaddr:$src, i32))]>, isPPC64;
|
||||
def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
|
||||
"lwzx $rD, $src", LdStGeneral,
|
||||
[(set GPRC:$rD, (load xaddr:$src))]>;
|
||||
def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src),
|
||||
"ldx $rD, $src", LdStLD,
|
||||
[(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
|
||||
def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
|
||||
"lvebx $vD, $base, $rA", LdStGeneral,
|
||||
[]>;
|
||||
@ -421,9 +437,9 @@ def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
|
||||
def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
|
||||
"lvewx $vD, $base, $rA", LdStGeneral,
|
||||
[]>;
|
||||
def LVX : XForm_1<31, 103, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
|
||||
"lvx $vD, $base, $rA", LdStGeneral,
|
||||
[]>;
|
||||
def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
|
||||
"lvx $vD, $src", LdStGeneral,
|
||||
[(set VRRC:$vD, (load xoaddr:$src))]>;
|
||||
}
|
||||
def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
|
||||
"lvsl $vD, $base, $rA", LdStGeneral,
|
||||
@ -489,15 +505,15 @@ def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
|
||||
"sraw $rA, $rS, $rB", IntShift,
|
||||
[(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
|
||||
let isStore = 1 in {
|
||||
def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"stbx $rS, $rA, $rB", LdStGeneral,
|
||||
[]>;
|
||||
def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"sthx $rS, $rA, $rB", LdStGeneral,
|
||||
[]>;
|
||||
def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"stwx $rS, $rA, $rB", LdStGeneral,
|
||||
[]>;
|
||||
def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst),
|
||||
"stbx $rS, $dst", LdStGeneral,
|
||||
[(truncstore GPRC:$rS, xaddr:$dst, i8)]>;
|
||||
def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst),
|
||||
"sthx $rS, $dst", LdStGeneral,
|
||||
[(truncstore GPRC:$rS, xaddr:$dst, i16)]>;
|
||||
def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst),
|
||||
"stwx $rS, $dst", LdStGeneral,
|
||||
[(store GPRC:$rS, xaddr:$dst)]>;
|
||||
def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"stwux $rS, $rA, $rB", LdStGeneral,
|
||||
[]>;
|
||||
@ -516,9 +532,9 @@ def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"stvewx $rS, $rA, $rB", LdStGeneral,
|
||||
[]>;
|
||||
def STVX : XForm_8<31, 231, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
|
||||
"stvx $rS, $rA, $rB", LdStGeneral,
|
||||
[]>;
|
||||
def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
|
||||
"stvx $rS, $dst", LdStGeneral,
|
||||
[(store VRRC:$rS, xoaddr:$dst)]>;
|
||||
}
|
||||
def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
|
||||
"srawi $rA, $rS, $SH", IntShift,
|
||||
@ -555,12 +571,12 @@ def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
|
||||
"fcmpu $crD, $fA, $fB", FPCompare>;
|
||||
|
||||
let isLoad = 1 in {
|
||||
def LFSX : XForm_25<31, 535, (ops F4RC:$dst, GPRC:$base, GPRC:$index),
|
||||
"lfsx $dst, $base, $index", LdStLFDU,
|
||||
[]>;
|
||||
def LFDX : XForm_25<31, 599, (ops F8RC:$dst, GPRC:$base, GPRC:$index),
|
||||
"lfdx $dst, $base, $index", LdStLFDU,
|
||||
[]>;
|
||||
def LFSX : XForm_25<31, 535, (ops F4RC:$frD, memrr:$src),
|
||||
"lfsx $frD, $src", LdStLFDU,
|
||||
[(set F4RC:$frD, (load xaddr:$src))]>;
|
||||
def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src),
|
||||
"lfdx $frD, $src", LdStLFDU,
|
||||
[(set F8RC:$frD, (load xaddr:$src))]>;
|
||||
}
|
||||
def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
|
||||
"fcfid $frD, $frB", FPGeneral,
|
||||
@ -614,12 +630,15 @@ def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
|
||||
|
||||
|
||||
let isStore = 1 in {
|
||||
def STFSX : XForm_28<31, 663, (ops F4RC:$frS, GPRC:$rA, GPRC:$rB),
|
||||
"stfsx $frS, $rA, $rB", LdStUX,
|
||||
[]>;
|
||||
def STFDX : XForm_28<31, 727, (ops F8RC:$frS, GPRC:$rA, GPRC:$rB),
|
||||
"stfdx $frS, $rA, $rB", LdStUX,
|
||||
def STFIWX: XForm_28<31, 983, (ops F4RC:$frS, memrr:$dst),
|
||||
"stfiwx $frS, $dst", LdStUX,
|
||||
[]>;
|
||||
def STFSX : XForm_28<31, 663, (ops F4RC:$frS, memrr:$dst),
|
||||
"stfsx $frS, $dst", LdStUX,
|
||||
[(store F4RC:$frS, xaddr:$dst)]>;
|
||||
def STFDX : XForm_28<31, 727, (ops F8RC:$frS, memrr:$dst),
|
||||
"stfdx $frS, $dst", LdStUX,
|
||||
[(store F8RC:$frS, xaddr:$dst)]>;
|
||||
}
|
||||
|
||||
// XL-Form instructions. condition register logical ops.
|
||||
@ -1012,6 +1031,27 @@ def : Pat<(srl GPRC:$rS, GPRC:$rB),
|
||||
def : Pat<(shl GPRC:$rS, GPRC:$rB),
|
||||
(SLW GPRC:$rS, GPRC:$rB)>;
|
||||
|
||||
def : Pat<(i32 (zextload iaddr:$src, i1)),
|
||||
(LBZ iaddr:$src)>;
|
||||
def : Pat<(i32 (zextload xaddr:$src, i1)),
|
||||
(LBZX xaddr:$src)>;
|
||||
def : Pat<(i32 (extload iaddr:$src, i1)),
|
||||
(LBZ iaddr:$src)>;
|
||||
def : Pat<(i32 (extload xaddr:$src, i1)),
|
||||
(LBZX xaddr:$src)>;
|
||||
def : Pat<(i32 (extload iaddr:$src, i8)),
|
||||
(LBZ iaddr:$src)>;
|
||||
def : Pat<(i32 (extload xaddr:$src, i8)),
|
||||
(LBZX xaddr:$src)>;
|
||||
def : Pat<(i32 (extload iaddr:$src, i16)),
|
||||
(LHZ iaddr:$src)>;
|
||||
def : Pat<(i32 (extload xaddr:$src, i16)),
|
||||
(LHZX xaddr:$src)>;
|
||||
def : Pat<(f64 (extload iaddr:$src, f32)),
|
||||
(FMRSD (LFS iaddr:$src))>;
|
||||
def : Pat<(f64 (extload xaddr:$src, f32)),
|
||||
(FMRSD (LFSX xaddr:$src))>;
|
||||
|
||||
// Same as above, but using a temporary. FIXME: implement temporaries :)
|
||||
/*
|
||||
def : Pattern<(xor GPRC:$in, imm:$imm),
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user