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[AVX-512] Promote AND/OR/XOR to v2i64/v4i64/v8i64 even when we have AVX512F/AVX512VL.
Previously we weren't creating masked logical operations if bitcasts appeared between the logic operation and the select. The IR optimizers can move bitcasts across logic operations and create these cases. To minimize the number of cases we need to handle, this change promotes all logic ops to an i64 vector type just like when only SSE or AVX is available. Unfortunately, this also has the consequence of making it difficult to select unmasked VPANDD/VPORD/VPXORD in all the cases it was previously used. This is the cause of most of the test change. This shouldn't result in any functional change though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279929 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
2e47cee376
commit
800ba955e3
@ -1345,13 +1345,17 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::SRL, VT, Custom);
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setOperationAction(ISD::SHL, VT, Custom);
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setOperationAction(ISD::SRA, VT, Custom);
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setOperationAction(ISD::AND, VT, Legal);
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setOperationAction(ISD::OR, VT, Legal);
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setOperationAction(ISD::XOR, VT, Legal);
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setOperationAction(ISD::CTPOP, VT, Custom);
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setOperationAction(ISD::CTTZ, VT, Custom);
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}
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// Need to promote to 64-bit even though we have 32-bit masked instructions
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// because the IR optimizers rearrange bitcasts around logic ops leaving
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// too many variations to handle if we don't promote them.
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setOperationPromotedToType(ISD::AND, MVT::v16i32, MVT::v8i64);
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setOperationPromotedToType(ISD::OR, MVT::v16i32, MVT::v8i64);
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setOperationPromotedToType(ISD::XOR, MVT::v16i32, MVT::v8i64);
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if (Subtarget.hasCDI()) {
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setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
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setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
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@ -1561,12 +1565,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
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setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
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for (auto VT : { MVT::v4i32, MVT::v8i32 }) {
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setOperationAction(ISD::AND, VT, Legal);
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setOperationAction(ISD::OR, VT, Legal);
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setOperationAction(ISD::XOR, VT, Legal);
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}
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for (auto VT : { MVT::v2i64, MVT::v4i64 }) {
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setOperationAction(ISD::SMAX, VT, Legal);
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setOperationAction(ISD::UMAX, VT, Legal);
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@ -28479,9 +28477,7 @@ static SDValue combineANDXORWithAllOnesIntoANDNP(SDNode *N, SelectionDAG &DAG) {
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SDValue N1 = N->getOperand(1);
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SDLoc DL(N);
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if (VT != MVT::v2i64 && VT != MVT::v4i64 &&
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VT != MVT::v8i64 && VT != MVT::v16i32 &&
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VT != MVT::v4i32 && VT != MVT::v8i32) // Legal with VLX
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if (VT != MVT::v2i64 && VT != MVT::v4i64 && VT != MVT::v8i64)
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return SDValue();
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// Canonicalize XOR to the left.
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@ -122,6 +122,10 @@ class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
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RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
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// A vector tye of the same width with element type i64. This is used to
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// create patterns for logic ops.
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ValueType i64VT = !cast<ValueType>("v" # !srl(Size, 6) # "i64");
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// A vector type of the same width with element type i32. This is used to
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// create the canonical constant zero node ImmAllZerosV.
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ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
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@ -387,6 +391,27 @@ multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
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Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
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AttSrcAsm, IntelSrcAsm, [],[]>;
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// This multiclass generates the unconditional/non-masking, the masking and
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// the zero-masking variant of the vector instruction. In the masking case, the
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// perserved vector elements come from a new dummy input operand tied to $dst.
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multiclass AVX512_maskable_logic<bits<8> O, Format F, X86VectorVTInfo _,
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dag Outs, dag Ins, string OpcodeStr,
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string AttSrcAsm, string IntelSrcAsm,
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dag RHS, dag MaskedRHS,
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InstrItinClass itin = NoItinerary,
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bit IsCommutable = 0, SDNode Select = vselect> :
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AVX512_maskable_custom<O, F, Outs, Ins,
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!con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
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!con((ins _.KRCWM:$mask), Ins),
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OpcodeStr, AttSrcAsm, IntelSrcAsm,
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[(set _.RC:$dst, RHS)],
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[(set _.RC:$dst,
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(Select _.KRCWM:$mask, MaskedRHS, _.RC:$src0))],
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[(set _.RC:$dst,
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(Select _.KRCWM:$mask, MaskedRHS,
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_.ImmAllZerosV))],
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"$src0 = $dst", itin, IsCommutable>;
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// Bitcasts between 512-bit vector types. Return the original type since
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// no instruction is needed for the conversion.
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def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
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@ -3860,17 +3885,102 @@ defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin,
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SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
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defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", umin,
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SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
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//===----------------------------------------------------------------------===//
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// AVX-512 Logical Instructions
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//===----------------------------------------------------------------------===//
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defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
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multiclass avx512_logic_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _, OpndItins itins,
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bit IsCommutable = 0> {
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defm rr : AVX512_maskable_logic<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(_.i64VT (OpNode (bitconvert (_.VT _.RC:$src1)),
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(bitconvert (_.VT _.RC:$src2)))),
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(_.VT (bitconvert (_.i64VT (OpNode _.RC:$src1,
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_.RC:$src2)))),
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itins.rr, IsCommutable>,
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AVX512BIBase, EVEX_4V;
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defm rm : AVX512_maskable_logic<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(_.i64VT (OpNode (bitconvert (_.VT _.RC:$src1)),
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(bitconvert (_.LdFrag addr:$src2)))),
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(_.VT (bitconvert (_.i64VT (OpNode _.RC:$src1,
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(bitconvert (_.LdFrag addr:$src2)))))),
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itins.rm>,
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AVX512BIBase, EVEX_4V;
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}
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multiclass avx512_logic_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _, OpndItins itins,
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bit IsCommutable = 0> :
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avx512_logic_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
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defm rmb : AVX512_maskable_logic<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
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"${src2}"##_.BroadcastStr##", $src1",
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"$src1, ${src2}"##_.BroadcastStr,
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(_.i64VT (OpNode _.RC:$src1,
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(bitconvert
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(_.VT (X86VBroadcast
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(_.ScalarLdFrag addr:$src2)))))),
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(_.VT (bitconvert (_.i64VT (OpNode _.RC:$src1,
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(bitconvert
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(_.VT (X86VBroadcast
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(_.ScalarLdFrag addr:$src2)))))))),
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itins.rm>,
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AVX512BIBase, EVEX_4V, EVEX_B;
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}
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multiclass avx512_logic_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
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AVX512VLVectorVTInfo VTInfo, OpndItins itins,
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Predicate prd, bit IsCommutable = 0> {
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let Predicates = [prd] in
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defm Z : avx512_logic_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
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IsCommutable>, EVEX_V512;
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let Predicates = [prd, HasVLX] in {
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defm Z256 : avx512_logic_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
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IsCommutable>, EVEX_V256;
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defm Z128 : avx512_logic_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
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IsCommutable>, EVEX_V128;
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}
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}
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multiclass avx512_logic_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
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OpndItins itins, Predicate prd,
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bit IsCommutable = 0> {
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defm NAME : avx512_logic_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
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itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
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}
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multiclass avx512_logic_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
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OpndItins itins, Predicate prd,
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bit IsCommutable = 0> {
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defm NAME : avx512_logic_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
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itins, prd, IsCommutable>,
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VEX_W, EVEX_CD8<64, CD8VF>;
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}
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multiclass avx512_logic_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
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SDNode OpNode, OpndItins itins, Predicate prd,
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bit IsCommutable = 0> {
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defm Q : avx512_logic_rm_vl_q<opc_q, OpcodeStr#"q", OpNode, itins, prd,
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IsCommutable>;
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defm D : avx512_logic_rm_vl_d<opc_d, OpcodeStr#"d", OpNode, itins, prd,
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IsCommutable>;
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}
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defm VPAND : avx512_logic_rm_vl_dq<0xDB, 0xDB, "vpand", and,
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SSE_INTALU_ITINS_P, HasAVX512, 1>;
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defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
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defm VPOR : avx512_logic_rm_vl_dq<0xEB, 0xEB, "vpor", or,
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SSE_INTALU_ITINS_P, HasAVX512, 1>;
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defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
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defm VPXOR : avx512_logic_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
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SSE_INTALU_ITINS_P, HasAVX512, 1>;
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defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
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defm VPANDN : avx512_logic_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
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SSE_INTALU_ITINS_P, HasAVX512, 0>;
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//===----------------------------------------------------------------------===//
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@ -7715,8 +7825,8 @@ multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
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defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", X86Abs>;
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def : Pat<(xor
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(bc_v16i32 (v16i1sextv16i32)),
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(bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
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(bc_v8i64 (v16i1sextv16i32)),
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(bc_v8i64 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
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(VPABSDZrr VR512:$src)>;
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def : Pat<(xor
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(bc_v8i64 (v8i1sextv8i64)),
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@ -945,17 +945,17 @@ define <8 x double> @test_maskz_broadcast_vaddpd(<8 x double> %i, double* %j,
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define <16 x float> @test_fxor(<16 x float> %a) {
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; AVX512F-LABEL: test_fxor:
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; AVX512F: ## BB#0:
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; AVX512F-NEXT: vpxord {{.*}}(%rip), %zmm0, %zmm0
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; AVX512F-NEXT: vpxorq {{.*}}(%rip), %zmm0, %zmm0
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; AVX512F-NEXT: retq
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;
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; AVX512VL-LABEL: test_fxor:
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; AVX512VL: ## BB#0:
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; AVX512VL-NEXT: vpxord {{.*}}(%rip), %zmm0, %zmm0
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; AVX512VL-NEXT: vpxorq {{.*}}(%rip), %zmm0, %zmm0
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; AVX512VL-NEXT: retq
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;
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; AVX512BW-LABEL: test_fxor:
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; AVX512BW: ## BB#0:
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; AVX512BW-NEXT: vpxord {{.*}}(%rip), %zmm0, %zmm0
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; AVX512BW-NEXT: vpxorq {{.*}}(%rip), %zmm0, %zmm0
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; AVX512BW-NEXT: retq
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;
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; AVX512DQ-LABEL: test_fxor:
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@ -1015,17 +1015,17 @@ declare <8 x double> @llvm.fabs.v8f64(<8 x double> %p)
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define <16 x float> @fabs_v16f32(<16 x float> %p)
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; AVX512F-LABEL: fabs_v16f32:
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; AVX512F: ## BB#0:
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; AVX512F-NEXT: vpandd {{.*}}(%rip), %zmm0, %zmm0
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; AVX512F-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
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; AVX512F-NEXT: retq
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;
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; AVX512VL-LABEL: fabs_v16f32:
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; AVX512VL: ## BB#0:
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; AVX512VL-NEXT: vpandd {{.*}}(%rip), %zmm0, %zmm0
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; AVX512VL-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
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; AVX512VL-NEXT: retq
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;
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; AVX512BW-LABEL: fabs_v16f32:
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; AVX512BW: ## BB#0:
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; AVX512BW-NEXT: vpandd {{.*}}(%rip), %zmm0, %zmm0
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; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
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; AVX512BW-NEXT: retq
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;
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; AVX512DQ-LABEL: fabs_v16f32:
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@ -430,12 +430,17 @@ define <8 x double> @masked_xor_v8f64(<8 x double> %a, <8 x double> %b, <8 x dou
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}
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define <8 x i64> @test_mm512_mask_and_epi32(<8 x i64> %__src, i16 zeroext %__k, <8 x i64> %__a, <8 x i64> %__b) {
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; ALL-LABEL: test_mm512_mask_and_epi32:
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; ALL: ## BB#0: ## %entry
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; ALL-NEXT: vpandq %zmm2, %zmm1, %zmm1
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; ALL-NEXT: kmovw %edi, %k1
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; ALL-NEXT: vpblendmd %zmm1, %zmm0, %zmm0 {%k1}
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; ALL-NEXT: retq
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; KNL-LABEL: test_mm512_mask_and_epi32:
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; KNL: ## BB#0: ## %entry
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; KNL-NEXT: kmovw %edi, %k1
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; KNL-NEXT: vpandd %zmm2, %zmm1, %zmm0 {%k1}
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; KNL-NEXT: retq
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;
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; SKX-LABEL: test_mm512_mask_and_epi32:
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; SKX: ## BB#0: ## %entry
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; SKX-NEXT: kmovw %edi, %k1
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; SKX-NEXT: vandps %zmm2, %zmm1, %zmm0 {%k1}
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; SKX-NEXT: retq
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entry:
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%and1.i.i = and <8 x i64> %__a, %__b
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%0 = bitcast <8 x i64> %and1.i.i to <16 x i32>
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@ -447,12 +452,17 @@ entry:
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}
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define <8 x i64> @test_mm512_mask_or_epi32(<8 x i64> %__src, i16 zeroext %__k, <8 x i64> %__a, <8 x i64> %__b) {
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; ALL-LABEL: test_mm512_mask_or_epi32:
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; ALL: ## BB#0: ## %entry
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; ALL-NEXT: vporq %zmm2, %zmm1, %zmm1
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; ALL-NEXT: kmovw %edi, %k1
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; ALL-NEXT: vpblendmd %zmm1, %zmm0, %zmm0 {%k1}
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; ALL-NEXT: retq
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; KNL-LABEL: test_mm512_mask_or_epi32:
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; KNL: ## BB#0: ## %entry
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; KNL-NEXT: kmovw %edi, %k1
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; KNL-NEXT: vpord %zmm2, %zmm1, %zmm0 {%k1}
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; KNL-NEXT: retq
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;
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; SKX-LABEL: test_mm512_mask_or_epi32:
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; SKX: ## BB#0: ## %entry
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; SKX-NEXT: kmovw %edi, %k1
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; SKX-NEXT: vorps %zmm2, %zmm1, %zmm0 {%k1}
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; SKX-NEXT: retq
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entry:
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%or1.i.i = or <8 x i64> %__a, %__b
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%0 = bitcast <8 x i64> %or1.i.i to <16 x i32>
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@ -464,12 +474,17 @@ entry:
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}
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define <8 x i64> @test_mm512_mask_xor_epi32(<8 x i64> %__src, i16 zeroext %__k, <8 x i64> %__a, <8 x i64> %__b) {
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; ALL-LABEL: test_mm512_mask_xor_epi32:
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; ALL: ## BB#0: ## %entry
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; ALL-NEXT: vpxorq %zmm2, %zmm1, %zmm1
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; ALL-NEXT: kmovw %edi, %k1
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; ALL-NEXT: vpblendmd %zmm1, %zmm0, %zmm0 {%k1}
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; ALL-NEXT: retq
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; KNL-LABEL: test_mm512_mask_xor_epi32:
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; KNL: ## BB#0: ## %entry
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; KNL-NEXT: kmovw %edi, %k1
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; KNL-NEXT: vpxord %zmm2, %zmm1, %zmm0 {%k1}
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; KNL-NEXT: retq
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;
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; SKX-LABEL: test_mm512_mask_xor_epi32:
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; SKX: ## BB#0: ## %entry
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; SKX-NEXT: kmovw %edi, %k1
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; SKX-NEXT: vxorps %zmm2, %zmm1, %zmm0 {%k1}
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; SKX-NEXT: retq
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entry:
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%xor1.i.i = xor <8 x i64> %__a, %__b
|
||||
%0 = bitcast <8 x i64> %xor1.i.i to <16 x i32>
|
||||
|
||||
@ -10,7 +10,7 @@ define <16 x i32> @select00(i32 %a, <16 x i32> %b) nounwind {
|
||||
; CHECK-NEXT: ## BB#1:
|
||||
; CHECK-NEXT: vmovdqa64 %zmm0, %zmm1
|
||||
; CHECK-NEXT: LBB0_2:
|
||||
; CHECK-NEXT: vpxord %zmm1, %zmm0, %zmm0
|
||||
; CHECK-NEXT: vpxorq %zmm1, %zmm0, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%cmpres = icmp eq i32 %a, 255
|
||||
%selres = select i1 %cmpres, <16 x i32> zeroinitializer, <16 x i32> %b
|
||||
|
||||
@ -78,7 +78,7 @@ define <8 x double> @stack_fold_andnpd_zmm(<8 x double> %a0, <8 x double> %a1) {
|
||||
|
||||
define <16 x float> @stack_fold_andnps_zmm(<16 x float> %a0, <16 x float> %a1) {
|
||||
;CHECK-LABEL: stack_fold_andnps_zmm
|
||||
;CHECK: vpandnd {{-?[0-9]*}}(%rsp), {{%zmm[0-9][0-9]*}}, {{%zmm[0-9][0-9]*}} {{.*#+}} 64-byte Folded Reload
|
||||
;CHECK: vpandnq {{-?[0-9]*}}(%rsp), {{%zmm[0-9][0-9]*}}, {{%zmm[0-9][0-9]*}} {{.*#+}} 64-byte Folded Reload
|
||||
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
|
||||
%2 = bitcast <16 x float> %a0 to <16 x i32>
|
||||
%3 = bitcast <16 x float> %a1 to <16 x i32>
|
||||
@ -105,7 +105,7 @@ define <8 x double> @stack_fold_andpd_zmm(<8 x double> %a0, <8 x double> %a1) {
|
||||
|
||||
define <16 x float> @stack_fold_andps_zmm(<16 x float> %a0, <16 x float> %a1) {
|
||||
;CHECK-LABEL: stack_fold_andps_zmm
|
||||
;CHECK: vpandd {{-?[0-9]*}}(%rsp), {{%zmm[0-9][0-9]*}}, {{%zmm[0-9][0-9]*}} {{.*#+}} 64-byte Folded Reload
|
||||
;CHECK: vpandq {{-?[0-9]*}}(%rsp), {{%zmm[0-9][0-9]*}}, {{%zmm[0-9][0-9]*}} {{.*#+}} 64-byte Folded Reload
|
||||
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
|
||||
%2 = bitcast <16 x float> %a0 to <16 x i32>
|
||||
%3 = bitcast <16 x float> %a1 to <16 x i32>
|
||||
@ -295,7 +295,7 @@ define <8 x double> @stack_fold_orpd_zmm(<8 x double> %a0, <8 x double> %a1) {
|
||||
|
||||
define <16 x float> @stack_fold_orps_zmm(<16 x float> %a0, <16 x float> %a1) {
|
||||
;CHECK-LABEL: stack_fold_orps_zmm
|
||||
;CHECK: vpord {{-?[0-9]*}}(%rsp), {{%zmm[0-9][0-9]*}}, {{%zmm[0-9][0-9]*}} {{.*#+}} 64-byte Folded Reload
|
||||
;CHECK: vporq {{-?[0-9]*}}(%rsp), {{%zmm[0-9][0-9]*}}, {{%zmm[0-9][0-9]*}} {{.*#+}} 64-byte Folded Reload
|
||||
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
|
||||
%2 = bitcast <16 x float> %a0 to <16 x i32>
|
||||
%3 = bitcast <16 x float> %a1 to <16 x i32>
|
||||
@ -375,7 +375,7 @@ define <8 x double> @stack_fold_xorpd_zmm(<8 x double> %a0, <8 x double> %a1) {
|
||||
|
||||
define <16 x float> @stack_fold_xorps_zmm(<16 x float> %a0, <16 x float> %a1) {
|
||||
;CHECK-LABEL: stack_fold_xorps_zmm
|
||||
;CHECK: vpxord {{-?[0-9]*}}(%rsp), {{%zmm[0-9][0-9]*}}, {{%zmm[0-9][0-9]*}} {{.*#+}} 64-byte Folded Reload
|
||||
;CHECK: vpxorq {{-?[0-9]*}}(%rsp), {{%zmm[0-9][0-9]*}}, {{%zmm[0-9][0-9]*}} {{.*#+}} 64-byte Folded Reload
|
||||
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
|
||||
%2 = bitcast <16 x float> %a0 to <16 x i32>
|
||||
%3 = bitcast <16 x float> %a1 to <16 x i32>
|
||||
|
||||
@ -124,7 +124,7 @@ define <4 x double> @stack_fold_andpd_ymm(<4 x double> %a0, <4 x double> %a1) {
|
||||
|
||||
define <4 x float> @stack_fold_andps(<4 x float> %a0, <4 x float> %a1) {
|
||||
;CHECK-LABEL: stack_fold_andps
|
||||
;CHECK: vpandd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
|
||||
;CHECK: vpandq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
|
||||
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
|
||||
%2 = bitcast <4 x float> %a0 to <4 x i32>
|
||||
%3 = bitcast <4 x float> %a1 to <4 x i32>
|
||||
@ -137,7 +137,7 @@ define <4 x float> @stack_fold_andps(<4 x float> %a0, <4 x float> %a1) {
|
||||
|
||||
define <8 x float> @stack_fold_andps_ymm(<8 x float> %a0, <8 x float> %a1) {
|
||||
;CHECK-LABEL: stack_fold_andps_ymm
|
||||
;CHECK: vpandd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
|
||||
;CHECK: vpandq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
|
||||
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
|
||||
%2 = bitcast <8 x float> %a0 to <8 x i32>
|
||||
%3 = bitcast <8 x float> %a1 to <8 x i32>
|
||||
@ -314,7 +314,7 @@ define <4 x double> @stack_fold_orpd_ymm(<4 x double> %a0, <4 x double> %a1) {
|
||||
|
||||
define <4 x float> @stack_fold_orps(<4 x float> %a0, <4 x float> %a1) {
|
||||
;CHECK-LABEL: stack_fold_orps
|
||||
;CHECK: vpord {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
|
||||
;CHECK: vporq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
|
||||
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
|
||||
%2 = bitcast <4 x float> %a0 to <4 x i32>
|
||||
%3 = bitcast <4 x float> %a1 to <4 x i32>
|
||||
@ -327,7 +327,7 @@ define <4 x float> @stack_fold_orps(<4 x float> %a0, <4 x float> %a1) {
|
||||
|
||||
define <8 x float> @stack_fold_orps_ymm(<8 x float> %a0, <8 x float> %a1) {
|
||||
;CHECK-LABEL: stack_fold_orps_ymm
|
||||
;CHECK: vpord {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
|
||||
;CHECK: vporq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
|
||||
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
|
||||
%2 = bitcast <8 x float> %a0 to <8 x i32>
|
||||
%3 = bitcast <8 x float> %a1 to <8 x i32>
|
||||
@ -398,7 +398,7 @@ define <4 x double> @stack_fold_xorpd_ymm(<4 x double> %a0, <4 x double> %a1) {
|
||||
|
||||
define <4 x float> @stack_fold_xorps(<4 x float> %a0, <4 x float> %a1) {
|
||||
;CHECK-LABEL: stack_fold_xorps
|
||||
;CHECK: vpxord {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
|
||||
;CHECK: vpxorq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload
|
||||
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
|
||||
%2 = bitcast <4 x float> %a0 to <4 x i32>
|
||||
%3 = bitcast <4 x float> %a1 to <4 x i32>
|
||||
@ -411,7 +411,7 @@ define <4 x float> @stack_fold_xorps(<4 x float> %a0, <4 x float> %a1) {
|
||||
|
||||
define <8 x float> @stack_fold_xorps_ymm(<8 x float> %a0, <8 x float> %a1) {
|
||||
;CHECK-LABEL: stack_fold_xorps_ymm
|
||||
;CHECK: vpxord {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
|
||||
;CHECK: vpxorq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}}, {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload
|
||||
%1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
|
||||
%2 = bitcast <8 x float> %a0 to <8 x i32>
|
||||
%3 = bitcast <8 x float> %a1 to <8 x i32>
|
||||
|
||||
@ -2041,12 +2041,12 @@ define <16 x i32> @test_bitreverse_v16i32(<16 x i32> %a) nounwind {
|
||||
; AVX512F-NEXT: vpsrld $24, %zmm0, %zmm1
|
||||
; AVX512F-NEXT: vpsrld $8, %zmm0, %zmm2
|
||||
; AVX512F-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm2, %zmm2
|
||||
; AVX512F-NEXT: vpord %zmm1, %zmm2, %zmm1
|
||||
; AVX512F-NEXT: vporq %zmm1, %zmm2, %zmm1
|
||||
; AVX512F-NEXT: vpslld $24, %zmm0, %zmm2
|
||||
; AVX512F-NEXT: vpslld $8, %zmm0, %zmm0
|
||||
; AVX512F-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm0, %zmm0
|
||||
; AVX512F-NEXT: vpord %zmm1, %zmm0, %zmm0
|
||||
; AVX512F-NEXT: vpord %zmm0, %zmm2, %zmm0
|
||||
; AVX512F-NEXT: vporq %zmm1, %zmm0, %zmm0
|
||||
; AVX512F-NEXT: vporq %zmm0, %zmm2, %zmm0
|
||||
; AVX512F-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm0, %zmm1
|
||||
; AVX512F-NEXT: vpslld $4, %zmm1, %zmm1
|
||||
; AVX512F-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm0, %zmm0
|
||||
|
||||
Loading…
Reference in New Issue
Block a user