[InstCombine] Add test cases for missing combines of phis with and/or/xor with constant argument. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299460 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2017-04-04 19:31:21 +00:00
parent 4dd33e6269
commit 80bfe66e42
3 changed files with 204 additions and 0 deletions

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@ -525,3 +525,71 @@ define <2 x i32> @test40vec2(i1 %C) {
%V = and <2 x i32> %A, <i32 123, i32 333>
ret <2 x i32> %V
}
define i32 @test41(i1 %which) {
; CHECK-LABEL: @test41(
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]]
; CHECK: delay:
; CHECK-NEXT: br label [[FINAL]]
; CHECK: final:
; CHECK-NEXT: [[A:%.*]] = phi i32 [ 104, [[ENTRY:%.*]] ], [ 10, [[DELAY]] ]
; CHECK-NEXT: ret i32 [[A]]
;
entry:
br i1 %which, label %final, label %delay
delay:
br label %final
final:
%A = phi i32 [ 1000, %entry ], [ 10, %delay ]
%value = and i32 %A, 123
ret i32 %value
}
define <2 x i32> @test41vec(i1 %which) {
; CHECK-LABEL: @test41vec(
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]]
; CHECK: delay:
; CHECK-NEXT: br label [[FINAL]]
; CHECK: final:
; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 1000, i32 1000>, [[ENTRY:%.*]] ], [ <i32 10, i32 10>, [[DELAY]] ]
; CHECK-NEXT: [[VALUE:%.*]] = and <2 x i32> [[A]], <i32 106, i32 106>
; CHECK-NEXT: ret <2 x i32> [[VALUE]]
;
entry:
br i1 %which, label %final, label %delay
delay:
br label %final
final:
%A = phi <2 x i32> [ <i32 1000, i32 1000>, %entry ], [ <i32 10, i32 10>, %delay ]
%value = and <2 x i32> %A, <i32 123, i32 123>
ret <2 x i32> %value
}
define <2 x i32> @test41vec2(i1 %which) {
; CHECK-LABEL: @test41vec2(
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]]
; CHECK: delay:
; CHECK-NEXT: br label [[FINAL]]
; CHECK: final:
; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 1000, i32 2500>, [[ENTRY:%.*]] ], [ <i32 10, i32 30>, [[DELAY]] ]
; CHECK-NEXT: [[VALUE:%.*]] = and <2 x i32> [[A]], <i32 123, i32 333>
; CHECK-NEXT: ret <2 x i32> [[VALUE]]
;
entry:
br i1 %which, label %final, label %delay
delay:
br label %final
final:
%A = phi <2 x i32> [ <i32 1000, i32 2500>, %entry ], [ <i32 10, i32 30>, %delay ]
%value = and <2 x i32> %A, <i32 123, i32 333>
ret <2 x i32> %value
}

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@ -733,3 +733,71 @@ define <2 x i32> @test49vec2(i1 %C) {
%V = or <2 x i32> %A, <i32 123, i32 333>
ret <2 x i32> %V
}
define i32 @test50(i1 %which) {
; CHECK-LABEL: @test50(
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]]
; CHECK: delay:
; CHECK-NEXT: br label [[FINAL]]
; CHECK: final:
; CHECK-NEXT: [[A:%.*]] = phi i32 [ 1019, [[ENTRY:%.*]] ], [ 123, [[DELAY]] ]
; CHECK-NEXT: ret i32 [[A]]
;
entry:
br i1 %which, label %final, label %delay
delay:
br label %final
final:
%A = phi i32 [ 1000, %entry ], [ 10, %delay ]
%value = or i32 %A, 123
ret i32 %value
}
define <2 x i32> @test50vec(i1 %which) {
; CHECK-LABEL: @test50vec(
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]]
; CHECK: delay:
; CHECK-NEXT: br label [[FINAL]]
; CHECK: final:
; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 1000, i32 1000>, [[ENTRY:%.*]] ], [ <i32 10, i32 10>, [[DELAY]] ]
; CHECK-NEXT: [[VALUE:%.*]] = or <2 x i32> [[A]], <i32 123, i32 123>
; CHECK-NEXT: ret <2 x i32> [[VALUE]]
;
entry:
br i1 %which, label %final, label %delay
delay:
br label %final
final:
%A = phi <2 x i32> [ <i32 1000, i32 1000>, %entry ], [ <i32 10, i32 10>, %delay ]
%value = or <2 x i32> %A, <i32 123, i32 123>
ret <2 x i32> %value
}
define <2 x i32> @test50vec2(i1 %which) {
; CHECK-LABEL: @test50vec2(
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]]
; CHECK: delay:
; CHECK-NEXT: br label [[FINAL]]
; CHECK: final:
; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 1000, i32 2500>, [[ENTRY:%.*]] ], [ <i32 10, i32 30>, [[DELAY]] ]
; CHECK-NEXT: [[VALUE:%.*]] = or <2 x i32> [[A]], <i32 123, i32 333>
; CHECK-NEXT: ret <2 x i32> [[VALUE]]
;
entry:
br i1 %which, label %final, label %delay
delay:
br label %final
final:
%A = phi <2 x i32> [ <i32 1000, i32 2500>, %entry ], [ <i32 10, i32 30>, %delay ]
%value = or <2 x i32> %A, <i32 123, i32 333>
ret <2 x i32> %value
}

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@ -384,3 +384,71 @@ define <2 x i32> @test29vec2(i1 %C) {
%V = xor <2 x i32> %A, <i32 123, i32 333>
ret <2 x i32> %V
}
define i32 @test30(i1 %which) {
; CHECK-LABEL: @test30(
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]]
; CHECK: delay:
; CHECK-NEXT: br label [[FINAL]]
; CHECK: final:
; CHECK-NEXT: [[A:%.*]] = phi i32 [ 915, [[ENTRY:%.*]] ], [ 113, [[DELAY]] ]
; CHECK-NEXT: ret i32 [[A]]
;
entry:
br i1 %which, label %final, label %delay
delay:
br label %final
final:
%A = phi i32 [ 1000, %entry ], [ 10, %delay ]
%value = xor i32 %A, 123
ret i32 %value
}
define <2 x i32> @test30vec(i1 %which) {
; CHECK-LABEL: @test30vec(
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]]
; CHECK: delay:
; CHECK-NEXT: br label [[FINAL]]
; CHECK: final:
; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 1000, i32 1000>, [[ENTRY:%.*]] ], [ <i32 10, i32 10>, [[DELAY]] ]
; CHECK-NEXT: [[VALUE:%.*]] = xor <2 x i32> [[A]], <i32 123, i32 123>
; CHECK-NEXT: ret <2 x i32> [[VALUE]]
;
entry:
br i1 %which, label %final, label %delay
delay:
br label %final
final:
%A = phi <2 x i32> [ <i32 1000, i32 1000>, %entry ], [ <i32 10, i32 10>, %delay ]
%value = xor <2 x i32> %A, <i32 123, i32 123>
ret <2 x i32> %value
}
define <2 x i32> @test30vec2(i1 %which) {
; CHECK-LABEL: @test30vec2(
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[WHICH:%.*]], label [[FINAL:%.*]], label [[DELAY:%.*]]
; CHECK: delay:
; CHECK-NEXT: br label [[FINAL]]
; CHECK: final:
; CHECK-NEXT: [[A:%.*]] = phi <2 x i32> [ <i32 1000, i32 2500>, [[ENTRY:%.*]] ], [ <i32 10, i32 30>, [[DELAY]] ]
; CHECK-NEXT: [[VALUE:%.*]] = xor <2 x i32> [[A]], <i32 123, i32 333>
; CHECK-NEXT: ret <2 x i32> [[VALUE]]
;
entry:
br i1 %which, label %final, label %delay
delay:
br label %final
final:
%A = phi <2 x i32> [ <i32 1000, i32 2500>, %entry ], [ <i32 10, i32 30>, %delay ]
%value = xor <2 x i32> %A, <i32 123, i32 333>
ret <2 x i32> %value
}