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[x86] add current codegen tests for PR27924

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272714 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjay Patel 2016-06-14 21:25:46 +00:00
parent 6edca03e84
commit 8291779372
1 changed files with 51 additions and 0 deletions
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test/CodeGen/X86/vector-compare-combines.ll Normal file
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE42
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
; FIXME: If we have SSE/AVX intrinsics in the code, we miss obvious combines
; unless we do them late on X86-specific nodes.
declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>)
define <4 x i32> @PR27924_cmpeq(<4 x i32> %a, <4 x i32> %b) {
; SSE-LABEL: PR27924_cmpeq:
; SSE: # BB#0:
; SSE-NEXT: pmaxsd %xmm1, %xmm0
; SSE-NEXT: pcmpeqd %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: PR27924_cmpeq:
; AVX: # BB#0:
; AVX-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
;
%cmp = icmp sgt <4 x i32> %a, %b
%max = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> %b
%sse_max = tail call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %a, <4 x i32> %b)
%truth = icmp eq <4 x i32> %max, %sse_max
%ret = sext <4 x i1> %truth to <4 x i32>
ret <4 x i32> %ret
}
define <4 x i32> @PR27924_cmpgt(<4 x i32> %a, <4 x i32> %b) {
; SSE-LABEL: PR27924_cmpgt:
; SSE: # BB#0:
; SSE-NEXT: pmaxsd %xmm1, %xmm0
; SSE-NEXT: pcmpgtd %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: PR27924_cmpgt:
; AVX: # BB#0:
; AVX-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpcmpgtd %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
;
%cmp = icmp sgt <4 x i32> %a, %b
%max = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> %b
%sse_max = tail call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %a, <4 x i32> %b)
%untruth = icmp sgt <4 x i32> %max, %sse_max
%ret = sext <4 x i1> %untruth to <4 x i32>
ret <4 x i32> %ret
}