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This code is no longer needed, it is moved to the target-indep code

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23332 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-09-13 19:31:44 +00:00
parent fa57702388
commit 82da52299c
2 changed files with 0 additions and 49 deletions
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24
lib/Target/Alpha/AlphaISelPattern.cpp
View File

@ -116,8 +116,6 @@ public:
CCInvMap.clear(); CCInvMap.clear();
} }
virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
unsigned SelectExpr(SDOperand N); unsigned SelectExpr(SDOperand N);
void Select(SDOperand N); void Select(SDOperand N);
@ -135,28 +133,6 @@ public:
}; };
} }
void AlphaISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
// If this function has live-in values, emit the copies from pregs to vregs at
// the top of the function, before anything else.
MachineBasicBlock *BB = MF.begin();
if (MF.livein_begin() != MF.livein_end()) {
SSARegMap *RegMap = MF.getSSARegMap();
for (MachineFunction::livein_iterator LI = MF.livein_begin(),
E = MF.livein_end(); LI != E; ++LI) {
const TargetRegisterClass *RC = RegMap->getRegClass(LI->second);
if (RC == Alpha::GPRCRegisterClass) {
BuildMI(BB, Alpha::BIS, 2, LI->second).addReg(LI->first)
.addReg(LI->first);
} else if (RC == Alpha::FPRCRegisterClass) {
BuildMI(BB, Alpha::CPYS, 2, LI->second).addReg(LI->first)
.addReg(LI->first);
} else {
assert(0 && "Unknown regclass!");
}
}
}
}
static bool isSIntImmediate(SDOperand N, int64_t& Imm) { static bool isSIntImmediate(SDOperand N, int64_t& Imm) {
// test for constant // test for constant
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {

25
lib/Target/X86/X86ISelPattern.cpp
View File

@ -1156,31 +1156,6 @@ static void EmitSpecialCodeForMain(MachineBasicBlock *BB,
} }
void ISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) { void ISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
// If this function has live-in values, emit the copies from pregs to vregs at
// the top of the function, before anything else.
MachineBasicBlock *BB = MF.begin();
if (MF.livein_begin() != MF.livein_end()) {
SSARegMap *RegMap = MF.getSSARegMap();
for (MachineFunction::livein_iterator LI = MF.livein_begin(),
E = MF.livein_end(); LI != E; ++LI) {
const TargetRegisterClass *RC = RegMap->getRegClass(LI->second);
if (RC == X86::R8RegisterClass) {
BuildMI(BB, X86::MOV8rr, 1, LI->second).addReg(LI->first);
} else if (RC == X86::R16RegisterClass) {
BuildMI(BB, X86::MOV16rr, 1, LI->second).addReg(LI->first);
} else if (RC == X86::R32RegisterClass) {
BuildMI(BB, X86::MOV32rr, 1, LI->second).addReg(LI->first);
} else if (RC == X86::RFPRegisterClass) {
BuildMI(BB, X86::FpMOV, 1, LI->second).addReg(LI->first);
} else if (RC == X86::RXMMRegisterClass) {
BuildMI(BB, X86::MOVAPDrr, 1, LI->second).addReg(LI->first);
} else {
assert(0 && "Unknown regclass!");
}
}
}
// If this is main, emit special code for main. // If this is main, emit special code for main.
if (Fn.hasExternalLinkage() && Fn.getName() == "main") if (Fn.hasExternalLinkage() && Fn.getName() == "main")
EmitSpecialCodeForMain(BB, MF.getFrameInfo()); EmitSpecialCodeForMain(BB, MF.getFrameInfo());