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TableGen SubtargetEmitter fix to allow A9 and Swift to coexist.
Allow variants to be defined only for some processors on a target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178074 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1308,7 +1308,7 @@ void CodeGenSchedModels::inferFromRW(const IdxVec &OperWrites,
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const IdxVec &OperReads,
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unsigned FromClassIdx,
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const IdxVec &ProcIndices) {
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DEBUG(dbgs() << "INFER RW: ");
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DEBUG(dbgs() << "INFER RW proc("; dumpIdxVec(ProcIndices); dbgs() << ") ");
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// Create a seed transition with an empty PredTerm and the expanded sequences
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// of SchedWrites for the current SchedClass.
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@ -1650,6 +1650,13 @@ void CodeGenSchedClass::dump(const CodeGenSchedModels* SchedModels) const {
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}
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}
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dbgs() << "\n ProcIdx: "; dumpIdxVec(ProcIndices); dbgs() << '\n';
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if (!Transitions.empty()) {
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dbgs() << "\n Transitions for Proc ";
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for (std::vector<CodeGenSchedTransition>::const_iterator
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TI = Transitions.begin(), TE = Transitions.end(); TI != TE; ++TI) {
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dumpIdxVec(TI->ProcIndices);
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}
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}
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}
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void PredTransitions::dump() const {
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@ -850,7 +850,22 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
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SCDesc.ReadAdvanceIdx = 0;
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// A Variant SchedClass has no resources of its own.
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if (!SCI->Transitions.empty()) {
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bool HasVariants = false;
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for (std::vector<CodeGenSchedTransition>::const_iterator
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TI = SCI->Transitions.begin(), TE = SCI->Transitions.end();
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TI != TE; ++TI) {
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if (TI->ProcIndices[0] == 0) {
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HasVariants = true;
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break;
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}
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IdxIter PIPos = std::find(TI->ProcIndices.begin(),
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TI->ProcIndices.end(), ProcModel.Index);
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if (PIPos != TI->ProcIndices.end()) {
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HasVariants = true;
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break;
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}
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}
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if (HasVariants) {
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SCDesc.NumMicroOps = MCSchedClassDesc::VariantNumMicroOps;
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continue;
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}
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